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GRM42-2C0G561J200AQ

Description
CAPACITOR, CERAMIC, MULTILAYER, 200V, C0G, 0.00056uF, SURFACE MOUNT, 1210, CHIP
CategoryPassive components    capacitor   
File Size236KB,6 Pages
ManufacturerMurata
Websitehttps://www.murata.com
Environmental Compliance
Download Datasheet Parametric View All

GRM42-2C0G561J200AQ Overview

CAPACITOR, CERAMIC, MULTILAYER, 200V, C0G, 0.00056uF, SURFACE MOUNT, 1210, CHIP

GRM42-2C0G561J200AQ Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerMurata
package instruction, 1210
Reach Compliance Codecompli
ECCN codeEAR99
capacitance0.00056 µF
Capacitor typeCERAMIC CAPACITOR
dielectric materialsCERAMIC
JESD-609 codee3
Manufacturer's serial numberGRM42-2
Installation featuresSURFACE MOUNT
multi-layerYes
negative tolerance5%
Number of terminals2
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package shapeRECTANGULAR PACKAGE
method of packingTR, PAPER, 7 INCH
positive tolerance5%
Rated (DC) voltage (URdc)200 V
size code1210
surface mountYES
Temperature characteristic codeC0G
Temperature Coefficient-/+30ppm/Cel ppm/°C
Terminal surfaceTin (Sn) - with Nickel (Ni) barrie
Terminal shapeWRAPAROUND
SURFACE MOUNT MONOLITHIC CHIP CAPACITORS
COG AND TEMPERATURE COMPENSATING TYPES
GRM36/39/40/42-6/42-2/43-2/44-1 Series
FEATURES
I
Miniature size
I
No Polarity
I
Nickel Barrier Termination Standard – highly resistant to
metal migration
I
Uniform dimensions and configuration
I
Suitable for reflow soldering
I
GRM39, 40 and 42-6 suitable for wave soldering
I
Minimum series inductance
I
Tape and Reel Packaging
I
Bulk Case Packaging available for GRM40 and smaller
I
Wide selection of capacitance values and voltages
I
Largest production capacity and volume in the world
SURFACE MOUNT
MONOLITHIC CHIP
CAPACITORS
PART NUMBERING SYSTEM
GRM40
–––
COG
101
J
050
A
D
CAPACITOR
TYPE AND SIZE
See below and
following pages.
3-digit code
appears as
necessary
to indicate
special
thickness
requirements.
Please consult
your local
sales office
for details.
TEMPERATURE
CHARACTERISTICS
COG
COH
P2H
R2H
S2H
T2H
U2J
SL
CAPACITANCE VALUE
Expressed in picofarads
and identified by a
three-digit number.
First two digits
represent significant
figures. Last digit
specifies the number
of zeros to follow.
For fractional values
below 10pF, the letter “R”
is used as the decimal
point and the last digit
becomes significant.
CAPACITANCE
TOLERANCE
*= Standard
5pf:
B = ±.1pf
*C = ±.25pf
>5pf to 10pf:
B = ±.1pf
C = ±.25pf
*D = ±.5pf
>10pf:
K = ±10%
*J = ±5%
G = ±2%
F = ±1%
VOLTAGE
Identified
by a
three-digit
number.
MARKING
A = Unmarked
PACKAGING
Reel Diameter/
Tape Material
Code
7” Paper Tape
D
7” Plastic Tape
L
13” Paper Tape
J
13” Plastic Tape
K
Bulk
B
Bulk Cassette
C
7” Paper
Q
2mm pitch
See pages 115 -118 for labeling and
packaging information.
CHIP DIMENSIONS
Dimensions: mm
Size
GRM36
GRM39*
e
g
e
EIA
Code
0402
0603
0805
L
Length
1.0 ± 0.05
1.6 ± 0.1
2.0 ± 0.1
3.2 ± 0.15
3.2 ± 0.2
W
Width
0.5 ± 0.05
0.8 ± 0.1
1.25 ± 0.1
1.6 ± 0.15
1.6 ± 0.2
2.5 ± 0.2
3.2 ± 0.3
5.0 ± 0.4
GRM40
GRM42-6
T
L
W
1206
GRM42-2
GRM43-2
GRM44-1
1210
1812
2220
3.2 ± 0.3
4.5 ± 0.4
5.7 ± 0.4
T
Thickness
0.5 ± 0.05
0.8 ± 0.1
0.6 ± 0.1
0.85 ± 0.1
1.25 ± 0.1
0.85 ± 0.1
1.15 ± 0.1
1.6 ± 0.2
1.15 ± 0.1
1.35 ± 0.15
1.8 ± 0.2
2.5 ± 0.2
2.0 max.
2.0 max.
e (min.)
Termination
0.15 ~ 0.3
0.2 ~ 0.5
0.2 ~ 0.7
g (min.)
Insulation
0.4
0.5
0.7
0.3 ~ 0.8
1.5
0.3 min.
0.3 min.
0.3 min.
1.0
2.0
2.0
*Bulk case packaging is L = 1.6 ± 0.07, W, T = 0.8 ± 0.07.
CHIP TERMINATION DIAGRAMS
Nickel Barrier Layer (Standard)
Ceramic Dielectric
Inner Electrode
GRM Series
Inner Termination (Ag or Ag/Pd or Cu)
Nickel Plated Barrier Layer
Tin Plating*
*Size 0402 – Solder Plated
All products on this page are available as standard through authorized Murata Electronics Distributors.
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