Features
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High Density, High Performance Electrically Erasable Complex
Programmable Logic Device
– 44-Pin, 32 I/O CPLD
– 7.5 ns Maximum Pin-to-Pin Delay
– Registered Operation Up To 125 MHz
– Fully Connected Input and Feedback Logic Array
– Backward Compatibility with ATF1500/L Software and Hardware
Flexible Logic Macrocell
D/T/Latch Configurable Flip Flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
Advanced Power Management Features
– Automatic 3 mA Stand-By (ATF1500AL)
– Pin-Controlled 5
µA
Stand-By Mode (Typical)
– Programmable Pin-Keeper Inputs and I/Os
Available in Commercial and Industrial Temperature Ranges
Available in 44-Pin PLCC and TQFP Packages
Advanced Flash Technology
– 100% Tested
– Completely Reprogrammable
– 100 Program/Erase Cycles
– 20 Year Data Retention
– 2000V ESD Protection
– 200 mA Latch-Up Immunity
Supported By Popular 3rd Party Tools
Security Fuse Feature
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•
High
Performance E
2
PLD
ATF1500A/AL
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Description
The ATF1500A is a high performance, high density Complex PLD. Built on an
advanced Flash technology, it has maximum pin to pin delays of 7.5 ns and supports
sequential logic operation at speeds up to 125 MHz. With 32 logic macrocells and up
to 36 inputs, it easily integrates logic from several TTL, SSI, MSI and classic PLDs.
The ATF1500A's global input and feedback architecture simplifies logic placement
and eliminates pinout changes due to design changes.
(continued)
Pin Configurations
Pin
Name
CLK
I
I/O
GCLR
OE1,
OE2
V
CC
PD
Function
Clock
Logic Inputs
Bidirectional
Buffers
Register Reset
(active low)
Output Enable
(active low)
+5V Supply
Power Down
(active high)
PLCC
INDEX
CORNER
TQFP
I/O
I/O
I/O/PD
VCC
OE2/I
GCLR/I
OE1/I
CLK/I
GND
I/O
I/O
44 42 40
38
36 34
43 41 39
37
35
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
1
2
3
4
5
6
7
8
9
10
11
13 15 17 19 21
12 14 16 18 20 22
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
33
32
31
30
29
28
27
26
25
24
23
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GND
I/O
Rev. 0759C–04/98
Top View
Top View
1
Functional Logic Diagram
(1)
Note:
1.
Arrows connecting macrocells indicate direction and groupings of CASIN/CASOUT data flow.
2
ATF1500A/AL
ATF1500A/AL
The ATF1500A has 32 bi-directional I/O pins and 4 dedi-
cated input pins. Each dedicated input pin can also serve
as a global control signal: register clock, register reset or
output enable. Each of these control signals can be
selected for use individually within each macrocell.
Each of the 32 logic macrocells generates a buried feed-
back, which goes to the global bus. Each input and I/O pin
also feeds into the global bus. Because of this global bus-
sing, each of these signals is always available to all 32
macrocells in the device.
Each macrocell also generates a foldback logic term, which
goes to a regional bus. All signals within a regional bus are
connected to all 16 macrocells within the region.
Cascade logic between macrocells in the ATF1500A allows
fast, efficient generation of complex logic functions. The
ATF1500A contains 4 such logic chains, each capable of
creating sum term logic with a fan in of up to 40 product
terms.
Speed/Power Management
The ATF1500A has several built-in speed and power man-
agement features. The ATF1500A contains circuitry that
automatically puts the device into a low power stand-by
mode when no logic transitions are occurring. This not only
reduces power consumption during inactive periods, but
also provides a proportional power savings for most appli-
cations running at system speeds below 10 MHz.
All ATF1500As also have an optional pin-controlled power
down mode. In this mode, current drops to below 10
µA.
When the power down option is selected, the PD pin is
used to power down the part. The power down option is
selected in the design source file. When enabled, the
device goes into power down when the PD pin is high. In
the power down mode, all internal logic signals are latched
and held, as are any enabled outputs. All pin transitions are
ignored until the PD is brought low. When the power down
feature is enabled, the PD cannot be used as a logic input
or output. However, the PD pin's macrocell may still be
used to generate buried foldback and cascade logic sig-
nals.
Each output also has individual slew rate control. This may
be used to reduce system noise by slowing down outputs
that do not need to operate at maximum speed. Outputs
default to slow switching, and may be specified as fast
switching in the design file.
Bus Friendly Pin-Keeper Input and I/O’s
All Input and I/O pins on the ATF1500A have programma-
ble “data keeper” circuits. If activated, when any pin is
driven high or low and then subsequently left floating, it will
stay at that previous high or low level.
This circuitry prevents unused Input and I/O lines from
floating to intermediate voltage levels, which cause unnec-
essary power consumption and system noise. The keeper
circuits eliminate the need for external pull-up resistors and
eliminate their DC power consumption.
Pin-keeper circuits can be disabled. Programming is con-
trolled in the logic design file. Once the pin-keeper circuits
are disabled, normal termination procedures are required
for unused inputs and I/Os.
Design Software Support
ATF1500A designs are supported by several 3rd party
tools. Automated fitters allow logic synthesis using a variety
of high level description languages and formats.
Input Diagram
V
CC
I/O Diagram
V
CC
OE
INPUT
100K
DATA
I/O
V
CC
ESD
PROTECTION
CIRCUIT
PROGRAMMABLE
OPTION
100K
PROGRAMMABLE
OPTION
3
ATF1500A/AL Macrocell
ATF1500A Macrocell
The ATF1500A macrocell is flexible enough to support
highly complex logic functions operating at high speed. The
macrocell consists of five sections: product terms and prod-
uct term select multiplexer; OR/XOR/CASCADE logic; a flip
flop; output select and enable; and logic array inputs.
routed to the OR gate, creating a five input AND/OR sum
term. With the addition of the CASIN from neighboring
macrocells, this can be expanded to as many as 40 product
terms with a very small additional delay.
The macrocell's XOR gate allows efficient implementation
of compare and arithmetic functions. One input to the XOR
comes from the OR sum term. The other XOR input can be
a product term or a fixed high or low level. For combinato-
rial outputs, the fixed level input allows output polarity
selection. For registered functions, the fixed levels allow De
Morgan minimization of the product terms. The XOR gate is
also used to emulate JK type flip flops.
Product Terms and Select Mux
Each ATF1500A macrocell has five product terms. Each
product term receives as its inputs all signals from both the
global bus and regional bus.
The product term select multiplexer (PTMUX) allocates the
five product terms as needed to the macrocell logic gates
and control signals. The PTMUX programming is deter-
mined by the design compiler, which selects the optimum
macrocell configuration.
Flip Flop
The ATF1500A's flip flop has very flexible data and control
functions. The data input can come from either the XOR
gate or from a separate product term. Selecting the sepa-
rate product term allows creation of a buried registered
feedback within a combinatorial output macrocell.
OR/XOR/CASCADE Logic
The ATF1500A macrocell's OR/XOR/CASCADE logic
structure is designed to efficiently support all types of logic.
Within a single macrocell, all the product terms can be
(continued)
4
ATF1500A/AL
ATF1500A/AL
In addition to D, T, JK and SR operation, the flip flop can
also be configured as a flow-through latch. In this mode,
data passes through when the clock is high and is latched
when the clock is low.
The clock itself can be either the global CLK pin or an indi-
vidual product term. The flip flop changes state on the
clock's rising edge. When the CLK pin is used as the clock,
one of the macrocell product terms can be selected as a
clock enable. When the clock enable function is active and
the enable signal (product term) is low, all clock edges are
ignored.
The flip flop's asynchronous reset signal (AR) can be either
the pin global clear (GCLR), a product term, or always off.
AR can also be a logic OR of GCLR with a product term.
The asynchronous preset (AP) can be a product term or
always off.
The output enable multiplexer (MOE) controls the output
enable signals. Any buffer can be permanently enabled for
simple output operation. Buffers can also be permanently
disabled to allow use of the pin as an input. In this configu-
ration all the macrocell resources are still available, includ-
ing the buried feedback, expander and CASCADE logic.
The output enable for each macrocell can also be selected
as either of the two OE pins or as an individual product
term.
Global/Regional Busses
The global bus contains all Input and I/O pin signals as well
as the buried feedback signal from all 32 macrocells.
Together with the complement of each signal, this provides
a 68 bit bus as input to every product term. Having the
entire global bus available to each macrocell eliminates any
potential routing problems. With this architecture designs
can be modified without requiring pinout changes.
Each macrocell also generates a foldback product term.
This signal goes to the regional bus, and is available to 16
macrocells. The foldback is an inverse polarity of one of the
macrocell's product terms. The 16 foldback terms in each
region allow generation of high fan-in sum terms (up to 21
product terms) with a small additional delay.
Output Select and Enable
The ATF1500A macrocell output can be selected as regis-
tered or combinatorial. When the output is registered, the
same registered signal is fed back internally to the global
bus. When the output is combinatorial, the buried feedback
can be either the same combinatorial signal or it can be the
register output if the separate product term is chosen as
the flip flop input.
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