ATF1502AS-15AI44 datasheet, PDF

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ATF1502AS-15AI44: DescriptionEE PLD, 10 ns, PQCC44; CategoryProgrammable logic devices Programmable logic; File Size305KB，25 Pages; ManufacturerAtmel (Microchip)

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ATF1502AS-15AI44 Overview

EE PLD, 10 ns, PQCC44

ATF1502AS-15AI44 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	QFP
package instruction	TQFP, TQFP44,.47SQ,32
Contacts	44
Reach Compliance Code	unknow
Other features	YES
maximum clock frequency	100 MHz
In-system programmable	YES
JESD-30 code	S-PQFP-G44
JESD-609 code	e0
JTAG BST	YES
length	10 mm
Humidity sensitivity level	3
Dedicated input times
Number of I/O lines	32
Number of macro cells	32
Number of terminals	44
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	0 DEDICATED INPUTS, 32 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	TQFP
Encapsulate equivalent code	TQFP44,.47SQ,32
Package shape	SQUARE
Package form	FLATPACK, THIN PROFILE
Peak Reflow Temperature (Celsius)	240
power supply	3.3,5 V
Programmable logic type	EE PLD
propagation delay	15 ns
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	10 mm
Base Number Matches	1

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Features

•

High-density, High-performance, Electrically-erasable Complex Programmable

Logic Device

– 32 Macrocells

– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell

– 44 Pins

– 7.5 ns Maximum Pin-to-pin Delay

– Registered Operation up to 125 MHz

– Enhanced Routing Resources

In-System Programmability (ISP) via JTAG

Flexible Logic Macrocell

– D/T Latch Configurable Flip-flops

– Global and Individual Register Control Signals

– Global and Individual Output Enable

– Programmable Output Slew Rate

– Programmable Output Open Collector Option

– Maximum Logic Utilization by Burying a Register with a COM Output

Advanced Power Management Features

Automatic 10 µA Standby for “L” Version

Pin-controlled 1 mA Standby Mode

Programmable Pin-keeper Inputs and I/Os

Reduced-power Feature per Macrocell

Available in Commercial and Industrial Temperature Ranges

Available in 44-lead PLCC and TQFP

Advanced EEPROM Technology

– 100% Tested

– Completely Reprogrammable

– 10,000 Program/Erase Cycles

– 20-year Data Retention

– 2000V ESD Protection

– 200 mA Latch-up Immunity

JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported

PCI-compliant

Security Fuse Feature

•

High-

performance

EEPROM CPLD

ATF1502AS

ATF1502ASL

•

Enhanced Features

•

Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)

Output Enable Product Terms

D Latch Mode

Combinatorial Output with Registered Feedback within Any Macrocell

Three Global Clock Pins

ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O

(“L” versions)

Fast Registered Input from Product Term

Programmable “Pin-keeper” Option

Power-up Reset Option

Pull-up Option on JTAG Pins TMS and TDI

Advanced Power Management Features

– Input Transition Detection

– Power-down (“L” versions)

– Individual Macrocell Power Option

– Disable ITD on Global Clocks, Inputs and I/O

Rev. 0995J–PLD–09/02

ATF1502AS(L)

The clock itself can be either one of the Global CLK signals (GCK[0 : 2]) or an individual prod-

uct term. The flip-flop changes state on the clock’s rising edge. When the GCK signal is used

as the clock, one of the macrocell product terms can be selected as a clock enable. When the

clock enable function is active and the enable signal (product term) is low, all clock edges are

ignored. The flip-flop’s asynchronous reset signal (AR) can be either the Global Clear

(GCLEAR), a product term, or always off. AR can also be a logic OR of GCLEAR with a prod-

uct term. The asynchronous preset (AP) can be a product term or always off.

Extra Feedback

The ATF1502AS(L) macrocell output can be selected as registered or combinatorial. The

extra buried feedback signal can be either combinatorial or a registered signal regardless of

whether the output is combinatorial or registered. (This enhancement function is automatically

implemented by the fitter software.) Feedback of a buried combinatorial output allows the cre-

ation of a second latch within a macrocell.

The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be indi-

vidually configured as an input, output or for bi-directional operation. The output enable for

each macrocell can be selected from the true or compliment of the two output enable pins, a

subset of the I/O pins, or a subset of the I/O macrocells. This selection is automatically done

by the fitter software when the I/O is configured as an input, all macrocell resources are still

available, including the buried feedback, expander and cascade logic.

The global bus contains all input and I/O pin signals as well as the buried feedback signal from

all 32 macrocells. The switch matrix in each logic block receives as its inputs all signals from

the global bus. Under software control, up to 40 of these signals can be selected as inputs to

the logic block.

Each macrocell also generates a foldback product term. This signal goes to the regional bus

and is available to four macrocells. The foldback is an inverse polarity of one of the macrocell’s

product terms. The four foldback terms in each region allow generation of high fan-in sum

terms (up to nine product terms) with little additional delay.

The ATF1502AS offers the option of programming all input and I/O pins so that pin-keeper cir-

cuits can be utilized. When any pin is driven high or low and then subsequently left floating, it

will stay at that previous high or low level. This circuitry prevents unused input and I/O lines

from floating to intermediate voltage levels, which causes unnecessary power consumption

and system noise. The keeper circuits eliminate the need for external pull-up resistors and

eliminate their DC power consumption.

I/O Control

Global Bus/Switch

Matrix

Foldback Bus

Programmable

Pin-keeper

Option for

Inputs and I/Os

0995J–PLD–09/02

ATF1502AS-15AI44 Related Products

	ATF1502AS-15AI44	ATF1502AS-10JC444	ATF1502AS-15JC44	ATF1502ASL-25JC44	ATF1502ASL-25AI44	ATF1502ASL-25JI44	ATFI1502AS
Description	EE PLD, 10 ns, PQCC44	EE PLD, 10 ns, PQCC44	EE PLD, 10 ns, PQCC44	EE PLD, 10 ns, PQCC44	EE PLD, 10 ns, PQCC44	EE PLD, 10 ns, PQCC44	EE PLD, 10 ns, PQCC44
Number of terminals	44	44	44	44	44	44	44
Maximum operating temperature	85 °C	70 °C	70 °C	70 °C	85 °C	85 °C	70 Cel
Minimum operating temperature	-40 °C	-	-	-	-40 °C	-40 °C	0.0 Cel
organize	0 DEDICATED INPUTS, 32 I/O	0 DEDICATED INPUTS, 32 I/O	0 DEDICATED INPUTS, 32 I/O	0 DEDICATED INPUTS, 32 I/O	0 DEDICATED INPUTS, 32 I/O	0 DEDICATED INPUTS, 32 I/O	0 DEDICATED INPUTS, 32 I/O
Output function	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL
Programmable logic type	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD
surface mount	YES	YES	YES	YES	YES	YES	Yes
Temperature level	INDUSTRIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL
Terminal form	GULL WING	J BEND	J BEND	J BEND	GULL WING	J BEND	J BEND
Terminal location	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	-
Parts packaging code	QFP	LCC	LPCC	LPCC	QFP	LPCC	-
package instruction	TQFP, TQFP44,.47SQ,32	QCCJ,	QCCJ, LDCC44,.7SQ	QCCJ, LDCC44,.7SQ	TQFP, TQFP44,.47SQ,32	QCCJ, LDCC44,.7SQ	-
Contacts	44	44	44	44	44	44	-
Reach Compliance Code	unknow	_compli	unknow	unknow	unknow	unknow	-
Other features	YES	-	YES	YES	YES	YES	-
maximum clock frequency	100 MHz	125 MHz	100 MHz	60 MHz	60 MHz	60 MHz	-
In-system programmable	YES	-	YES	YES	YES	YES	-
JESD-30 code	S-PQFP-G44	S-PQCC-J44	S-PQCC-J44	S-PQCC-J44	S-PQFP-G44	S-PQCC-J44	-
JESD-609 code	e0	e0	e0	e0	e0	e0	-
JTAG BST	YES	-	YES	YES	YES	YES	-
length	10 mm	16.5862 mm	16.586 mm	16.586 mm	10 mm	16.586 mm	-
Humidity sensitivity level	3	2	2	2	3	2	-
Number of I/O lines	32	32	32	32	32	32	-
Number of macro cells	32	-	32	32	32	32	-
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-
encapsulated code	TQFP	QCCJ	QCCJ	QCCJ	TQFP	QCCJ	-
Encapsulate equivalent code	TQFP44,.47SQ,32	-	LDCC44,.7SQ	LDCC44,.7SQ	TQFP44,.47SQ,32	LDCC44,.7SQ	-
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	-
Package form	FLATPACK, THIN PROFILE	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	FLATPACK, THIN PROFILE	CHIP CARRIER	-
Peak Reflow Temperature (Celsius)	240	225	225	225	240	225	-
power supply	3.3,5 V	-	3.3,5 V	3.3,5 V	3.3,5 V	3.3,5 V	-
propagation delay	15 ns	10 ns	15 ns	25 ns	25 ns	25 ns	-
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	-
Maximum seat height	1.2 mm	4.57 mm	4.572 mm	4.572 mm	1.2 mm	4.572 mm	-
Maximum supply voltage	5.5 V	5.25 V	5.25 V	5.25 V	5.5 V	5.5 V	-
Minimum supply voltage	4.5 V	4.75 V	4.75 V	4.75 V	4.5 V	4.5 V	-
Nominal supply voltage	5 V	5 V	5 V	5 V	5 V	5 V	-
technology	CMOS	-	CMOS	CMOS	CMOS	CMOS	-
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-
Terminal pitch	0.8 mm	1.27 mm	1.27 mm	1.27 mm	0.8 mm	1.27 mm	-
Maximum time at peak reflow temperature	30	30	30	30	30	30	-
width	10 mm	16.5862 mm	16.586 mm	16.586 mm	10 mm	16.586 mm	-
Base Number Matches	1	-	-	1	1	1	-
Maker	-	Atmel (Microchip)	Atmel (Microchip)	Atmel (Microchip)	Atmel (Microchip)	-	-

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