PF38F2020W0ZTQ1 datasheet, PDF

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PF38F2020W0ZTQ1: DescriptionMemory Circuit, 4MX16, CMOS, PBGA88, 8 X 10 MM, 1.20 MM HEIGHT, LEAD FREE, SCSP-88; Categorystorage storage; File Size671KB，46 Pages; ManufacturerNumonyx ( Micron ); Websitehttps://www.micron.com

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PF38F2020W0ZTQ1 Overview

Memory Circuit, 4MX16, CMOS, PBGA88, 8 X 10 MM, 1.20 MM HEIGHT, LEAD FREE, SCSP-88

PF38F2020W0ZTQ1 Parametric

Parameter Name	Attribute value
Maker	Numonyx ( Micron )
Parts packaging code	BGA
package instruction	TFBGA,
Contacts	88
Reach Compliance Code	unknow
Other features	CONTAINS 8 MBIT PSRAM
JESD-30 code	R-PBGA-B88
JESD-609 code	e1
length	10 mm
memory density	67108864 bi
Memory IC Type	MEMORY CIRCUIT
memory width	16
Number of functions	1
Number of terminals	88
word count	4194304 words
character code	4000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-25 °C
organize	4MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	8 mm

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Intel

Wireless Flash Memory

(W18/W30 SCSP)

32WQ and 64WQ Family with Asynchronous RAM

Datasheet

Product Features

■

Device Architecture

— Flash Density: 32-Mbit, 64-Mbit

— Async PSRAM Density: 8-, 16-, 32-Mbit

— Async SRAM Density: 4-, 8-, 16-Mbit

— Top, Bottom or Dual flash parameter

configuration

Device Voltage

— Flash V

= 1.8 V (90 nm or 130 nm)

— Flash V

CCQ

= 1.8 V (90 nm)

— Flash V

CCQ

= 1.8 V or 3.0 V (130 nm)

— RAM V

= 3.0 V

— RAM V

CCQ

= 1.8 V or 3.0 V

Device Packaging

— 88 balls (8 x 10 active ball matrix)

— Area: 8x10 mm

— Height: 1.2 mm to 1.4 mm

PSRAM Performance

— 88 ns initial access, 30 ns async page

reads at 1.8 V I/O

— 70 ns initial access, 25 ns async page

reads at 1.8 V I/O

— 85 ns initial access, 35 ns async page

reads at 3.0 V I/O

— 70 ns initial access, 25 ns async page

reads at 3.0 V I/O

SRAM Performance

— 70 ns initial access at 1.8 V or 3.0 V I/O

■

Flash Performance

— 65 ns initial access at 1.8 V I/O

— 70 ns initial access at 3.0 V I/O

— 25 ns async page at 1.8 V or 3.0 V I/O

— 14 ns sync reads (t

CHQV

) at 1.8 V I/O

— 20 ns sync reads (t

CHQV

) at 3.0 V I/O

— Enhanced Factory Programming:

3.10 µs/Word (Typ)

Flash Architecture

— Read-While-Write/Erase

— Asymmetrical blocking structure

— 4-KWord parameter blocks (Top or

Bottom)

— 32-KWord main blocks

— 4-Mbit partition size

— 128-bit One-Time Programmable (OTP)

Protection Register

— Zero-latency block locking

— Absolute write protection with block lock

using F-VPP and F-WP#

Flash Software

— Intel

Flash Data Integrator (FDI)

— Common Flash Interface (CFI)

Quality and Reliability

— Extended Temperature: –25 °C to +85 °C

— Minimum 100K flash block erase cycle

— 90 nm ETOX™ IX flash technology

— 130 nm ETOX™ VIII flash technology

The Intel® Wireless Flash Memory (W18/W30 SCSP) family offers a variety of flash plus static

RAM combinations in a common package footprint. The flash memory features 1.8 V low-power

operations with flexible, multi-partition, dual-operation Read-While-Write / Read-While-Erase,

asynchronous, and synchronous reads. This SCSP device integrates up to two flash die, one

PSRAM die, and one SRAM die in a low-profile package compatible with other SCSP families

with QUAD+ ballout.

Notice:

This document contains information on products in the sampling and initial production

phases of development. The specifications are subject to change without notice. Verify with

your local Intel sales office that you have the latest datasheet before finalizing a design.

251407-008

January 2005

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. EXCEPT AS PROVIDED IN INTEL’S TERMS

AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS

OR IMPLIED WARRANTY RELATING TO SALE AND/OR USE OF INTEL PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO

FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER

INTELLECTUAL PROPERTY RIGHT.

Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the

presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by

estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.

Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

IMPORTANT - PLEASE READ BEFORE INSTALLING OR USING INTEL® PRE-RELEASE PRODUCTS

Please review the terms at

http://www.intel.com/design/prerelease_terms.htm

carefully before using any Intel® pre-release product, including any

evaluation, development or reference hardware and/or software product (collectively, “Pre-Release Product”). By using the Pre-Release Product, you

indicate your acceptance of these terms, which constitute the agreement (the “Agreement”) between you and Intel Corporation (“Intel”). In the event

that you do not agree with any of these terms and conditions, do not use or install the Pre-Release Product and promptly return it unused to Intel.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel

(R)

IRELESS

LASH

EMORY

32WQ

AND

64WQ F

AMILY

may contain design defects or errors known as errata which may cause the product to

deviate from published specifications. Current characterized errata are available on request.

This Datasheet as well as the software described in it is furnished under license and may only be used or copied in accordance with the terms of the

license. The information in this manual is furnished for informational use only, is subject to change without notice, and should not be construed as a

commitment by Intel Corporation. Intel Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this

document or any software that may be provided in association with this document.

Except as permitted by such license, no part of this document may be reproduced, stored in a retrieval system, or transmitted in any form or by any

means without the express written consent of Intel Corporation.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling

1-800-548-4725 or by visiting Intel's website at

http://www.intel.com.

*Other names and brands may be claimed as the property of others.

Datasheet

Contents

1.0

Introduction....................................................................................................................................7

1.1

1.2

2.0

2.1

2.2

3.0

4.0

Nomenclature .......................................................................................................................7

Conventions..........................................................................................................................8

Block Diagram ......................................................................................................................9

Flash Memory Map and Partitioning ...................................................................................10

Functional Overview

.....................................................................................................................9

Package Information

...................................................................................................................12

Ballout and Signal Description

..................................................................................................14

4.1

4.2

Signal Ballout......................................................................................................................14

Signal Descriptions .............................................................................................................15

Absolute Maximum Ratings ................................................................................................17

Operating Conditions ..........................................................................................................18

DC Characteristics..............................................................................................................20

Flash AC Characteristics ....................................................................................................23

SRAM AC Characteristics...................................................................................................24

PSRAM AC Characteristics ................................................................................................26

Device AC Test Conditions .................................................................................................31

5.0

Maximum Ratings and Operating Conditions...........................................................................17

5.1

5.2

6.0

7.0

Electrical Specifications

.............................................................................................................20

6.1

7.1

7.2

7.3

7.4

AC Characteristics

......................................................................................................................23

8.0

9.0

Flash Power Consumption

.........................................................................................................31

Device Operation

.........................................................................................................................31

9.1

9.2

Bus Operations ...................................................................................................................31

Flash Command Definitions................................................................................................35

10.0 Flash Read Operations

...............................................................................................................35

11.0 Flash Program Operations

.........................................................................................................35

12.0 Flash Erase Operations

..............................................................................................................35

13.0 Flash Security Modes..................................................................................................................35

14.0 Flash Read Configuration Register

...........................................................................................35

15.0 SRAM Operations

........................................................................................................................36

15.1

15.2

16.1

16.2

Power-up Sequence and Initialization ................................................................................36

Data Retention Mode ..........................................................................................................36

Power-Up Sequence and Initialization ................................................................................38

Standby Mode/ Deep Power-Down Mode ..........................................................................40

16.0 PSRAM Operations......................................................................................................................38

Datasheet

PF38F2020W0ZTQ1 Related Products

	PF38F2020W0ZTQ1	PF38F2020W0ZBQ1
Description	Memory Circuit, 4MX16, CMOS, PBGA88, 8 X 10 MM, 1.20 MM HEIGHT, LEAD FREE, SCSP-88	Memory Circuit, 4MX16, CMOS, PBGA88, 8 X 10 MM, 1.20 MM HEIGHT, LEAD FREE, SCSP-88
Parts packaging code	BGA	BGA
package instruction	TFBGA,	TFBGA,
Contacts	88	88
Reach Compliance Code	unknow	unknown
Other features	CONTAINS 8 MBIT PSRAM	CONTAINS 8 MBIT PSRAM
JESD-30 code	R-PBGA-B88	R-PBGA-B88
JESD-609 code	e1	e1
length	10 mm	10 mm
memory density	67108864 bi	67108864 bit
Memory IC Type	MEMORY CIRCUIT	MEMORY CIRCUIT
memory width	16	16
Number of functions	1	1
Number of terminals	88	88
word count	4194304 words	4194304 words
character code	4000000	4000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-25 °C	-25 °C
organize	4MX16	4MX16
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TFBGA	TFBGA
Package shape	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260	260
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm
Maximum supply voltage (Vsup)	1.95 V	1.95 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	OTHER	OTHER
Terminal surface	TIN SILVER COPPER	TIN SILVER COPPER
Terminal form	BALL	BALL
Terminal pitch	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
width	8 mm	8 mm

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