SAF1760
Hi-Speed Universal Serial Bus host controller for embedded
applications
Rev. 2 — 19 June 2012
Product data sheet
1. General description
The SAF1760 is a Hi-Speed Universal Serial Bus (USB) host controller with a generic
processor interface. It integrates one Enhanced Host Controller Interface (EHCI), one
Transaction Translator (TT) and three transceivers. The host controller portion of the
SAF1760 and the three transceivers comply to
Ref. 1 “Universal Serial Bus Specification
Rev. 2.0”.
The EHCI portion of the SAF1760 is adapted from
Ref. 2 “Enhanced Host
Controller Interface Specification for Universal Serial Bus Rev. 1.0”.
The integrated high-performance Hi-Speed USB transceivers enable the SAF1760 to
handle all Hi-Speed USB transfer speed modes: high-speed (480 Mbit/s), full-speed
(12 Mbit/s) and low-speed (1.5 Mbit/s). The three downstream ports allow simultaneous
connection of three devices at different speeds (high-speed, full-speed and low-speed).
The generic processor interface allows the SAF1760 to be connected to various
processors as a memory-mapped resource. The SAF1760 is a slave host: it does not
require
bus-mastering
capabilities of the host system bus. The interface can be
configured, ensuring compatibility with a variety of processors. Data transfer can be
performed on 16 bits or 32 bits, using Programmed Input/Output (PIO) or Direct Memory
Access (DMA) with major control signals configurable as active LOW or active HIGH.
Integration of the TT allows connection to full-speed and low-speed devices, without the
need of integrating Open Host Controller Interface (OHCI) or Universal Host Controller
Interface (UHCI). Instead of dealing with two sets of software drivers, EHCI and OHCI or
UHCI, you need to deal with only one set, EHCI, that dramatically reduces software
complexity and IC cost.
2. Features and benefits
Automotive qualified in accordance with AEC-Q100
The host controller portion of the SAF1760 complies with
Ref. 1 “Universal Serial Bus
Specification Rev. 2.0”
The EHCI portion of the SAF1760 is adapted from
Ref. 2 “Enhanced Host Controller
Interface Specification for Universal Serial Bus Rev. 1.0”
Contains three integrated Hi-Speed USB transceivers that support high-speed,
full-speed and low-speed modes
Integrates a TT for original USB (full-speed and low-speed) device support
Up to 64 kB internal memory (8 k
×
64 bit) accessible through a generic processor
interface; operation in multitasking environments is made possible by the
implementation of virtual segmentation mechanism with bank switching on task
request
NXP Semiconductors
SAF1760
Embedded Hi-Speed USB host controller
Generic processor interface, non-multiplexed and variable latency, with a configurable
32-bit or 16-bit external data bus; the processor interface can be defined as
variable-latency or SRAM type (memory mapping)
Slave DMA support to reduce the load of the host system CPU during the data transfer
to or from the memory
Integrated Phase-Locked Loop (PLL) with a 12 MHz crystal or an external clock input
Integrated multi-configuration FIFO
Optimized
msec-based
or
multi-msec-based
Proprietary Transfer Descriptor (PTD)
interrupt
Tolerant I/O for low voltage CPU interface (1.65 V to 3.6 V)
3.3 V-to-5.0 V external power supply input
Integrated 5.0 V-to-1.8 V or 3.3 V-to-1.8 V voltage regulator (internal 1.8 V for
low-power core)
Internal power-on reset and low-voltage reset
Supports suspend and remote wake-up
Target current consumption:
Normal operation; one port in high-speed active: I
CC
< 100 mA
Suspend mode: I
CC(susp)
< 150
μA
at room temperature
Built-in configurable overcurrent circuitry (digital or analog overcurrent protection)
3. Applications
The SAF1760 can be used to implement a Hi-Speed USB compliant host controller
connected to most of the CPUs present in the market today, having a generic processor
interface with de-multiplexed address and data bus. This is because of the efficient
slave-type interface of the SAF1760.
This NXP USB product can only be used in automotive applications. Inclusion or use of
the NXP USB products in other than automotive applications is not permitted and for your
company’s own risk. Your company agrees to full indemnify NXP for any damages
resulting from such inclusion or use.
4. Ordering information
Table 1.
Ordering information
Name
SAF1760BE
LQFP128
Description
plastic low profile quad flat package; 128 leads; body 14
×
20
×
1.4 mm
Version
SOT425-1
Type number Package
SAF1760
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 19 June 2012
2 of 110
NXP Semiconductors
SAF1760
Embedded Hi-Speed USB host controller
5. Block diagram
V
CC(I/O)
37 to 39, 41 to 43,
45 to 47, 49, 51,
52, 54, 56 to 58,
60 to 62, 64 to 66,
68 to 70, 72 to 74,
76 to 78, 80
DATA[15:0]/DATA[31:0]
GENERIC PROCESSOR BUS
82, 84, 86, 87,
89, 91 to 93,
95 to 98,
100 to 103, 105
A[17:1]
CS_N
RD_N
106
107
10, 40, 48, 59, 67,
75, 83, 94, 104, 115
SAF1760BE
HC PTD MEMORY
(3 kB)
30 MHz
HC PAYLOAD
MEMORY (60 kB)
60 MHz
PLL
11
12
13
XTAL1
XTAL2
CLKIN
17
RISC PROCESSOR
16-bit
INTERFACE:
or
32-bit
MEMORY
MANAGEMENT
UNIT
+
INTERRUPT
CONTROL
+
SLAVE DMA
CONTROLLER
+
HARDWARE
CONFIGURATION
REGISTERS
GLOBAL CONTROL
AND POWER
MANAGEMENT
MEMORY
ARBITER
AND FIFO
122
119
RESET_N
SUSPEND/
WAKEUP_N
WR_N 108
IRQ
112
POWER-ON RESET
AND V
BAT
ON
110
5, 50,
85, 118
6, 7
BAT_ON_N
DREQ 114
DACK
116
TRANSACTION
TRANSLATOR
AND RAM
EHCI AND
OPERATIONAL
REGISTERS
PIE
5 V-TO-1.8 V
VOLTAGE
REGULATOR
5 V-TO-3.3 V
VOLTAGE
REGULATOR
REG1V8
V
CC(5V0)
9
REG3V3
USB FULL-SPEED AND LOW-SPEED DATA PATH
USB HIGH-SPEED DATA PATH
PORT ROUTING OR CONTROL LOGIC + HOST AND HUB PORT STATUS
DIGITAL
AND ANALOG
OVERCURRENT
DETECTION
2
REF5V
8
HI-SPEED
USB ATX1
HI-SPEED
USB ATX2
HI-SPEED
USB ATX3
4, 17, 24,
31, 123
GND(OSC)
GNDA
53, 88, 121
GNDC
14, 36, 44, 55, 63,
71, 79, 90, 99, 109
001aai632
16 15
20 19 18 21 127
23 22
27 26
25 28 128
30 29 34 33 32 35 1
RREF1
DP1
DM1
RREF2
OC1_N
DP2
DM2
RREF3
OC2_N
DP3
DM3
OC3_N
PSW3_N
GNDD
GNDA
GND
(RREF1)
GNDA
GND
(RREF2)
PSW1_N
PSW2_N
GND GNDA
(RREF3)
All ground pins should normally be connected to a common ground plane.
Fig 1.
Block diagram
SAF1760
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 19 June 2012
3 of 110
NXP Semiconductors
SAF1760
Embedded Hi-Speed USB host controller
6. Pinning information
6.1 Pinning
128
103
102
1
SAF1760BE
38
39
64
65
001aai633
Fig 2.
Pin configuration (LQFP128); top view
6.2 Pin description
Table 2.
Pin description
Pin
LQFP128
OC3_N
1
AI
port 3 analog (5 V input) and digital overcurrent input; if not
used, connect to V
CC(I/O)
through a 10 kΩ resistor
input, 5 V tolerant
REF5V
TEST1
GNDA
REG1V8
2
3
4
5
AI
I
G
P
5 V reference input for analog OC detector; connect a 100 nF
decoupling capacitor
connect to ground
analog ground
core power output (1.8 V); internal 1.8 V for the digital core;
used for decoupling; connect a 100 nF capacitor; for details on
additional capacitor placement, see
Section 7.8
input to internal regulators (3.0 V to 5.5 V); connect a 100 nF
decoupling capacitor; see
Section 7.8
input to internal regulators (3.0 V to 5.5 V); connect a 100 nF
decoupling capacitor; see
Section 7.8
oscillator ground
regulator output (3.3 V); for decoupling only; connect a 100 nF
capacitor and a 4.7
μF-to-10 μF
capacitor; see
Section 7.8
digital supply voltage; 1.65 V to 3.6 V; connect a 100 nF
decoupling capacitor; see
Section 7.8
12 MHz crystal connection input; connect to ground if an
external clock is used; see
Table 89
12 MHz crystal connection output
© NXP B.V. 2012. All rights reserved.
Symbol
[1][2]
Type
[3]
Description
V
CC(5V0)
V
CC(5V0)
GND(OSC)
REG3V3
V
CC(I/O)
XTAL1
XTAL2
SAF1760
6
7
8
9
10
11
12
P
P
G
P
P
AI
AO
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 2 — 19 June 2012
4 of 110
NXP Semiconductors
SAF1760
Embedded Hi-Speed USB host controller
Pin description
…continued
Pin
LQFP128
13
14
16
17
18
19
20
21
Type
[3]
Description
I
G
G
AI
G
AI/O
G
AI/O
OD
12 MHz oscillator or clock input; when not in use, connect to
V
CC(I/O)
digital ground
RREF1 ground
reference resistor connection; connect a 12 kΩ
±
1 % resistor
between this pin and the RREF1 ground
analog ground
downstream data minus port 1
analog ground
downstream data plus port 1
power switch port 1, active LOW
output pad, push-pull open-drain, 8 mA output drive, 5 V
tolerant
Table 2.
Symbol
[1][2]
CLKIN
GNDD
RREF1
GNDA
[4]
DM1
GNDA
DP1
PSW1_N
GND(RREF1) 15
GND(RREF2) 22
RREF2
GNDA
[5]
DM2
GNDA
DP2
PSW2_N
23
24
25
26
27
28
G
AI
G
AI/O
G
AI/O
OD
RREF2 ground
reference resistor connection; connect a 12 kΩ
±
1 % resistor
between this pin and the RREF2 ground
analog ground
downstream data minus port 2
analog ground
downstream data plus port 2
power switch port 2, active LOW
output pad, push-pull open-drain, 8 mA output drive, 5 V
tolerant
GND(RREF3) 29
RREF3
GNDA
[6]
DM3
GNDA
DP3
PSW3_N
30
31
32
33
34
35
G
AI
G
AI/O
G
AI/O
OD
RREF3 ground
reference resistor connection; connect a 12 kΩ
±
1 % resistor
between this pin and the RREF3 ground
analog ground
downstream data minus port 3
analog ground
downstream data plus port 3
power switch port 3, active LOW
output pad, push-pull open-drain, 8 mA output drive, 5 V
tolerant
GNDD
DATA0
36
37
G
I/O
digital ground
data bit 0 input and output
bidirectional pad, push-pull input, 3-state output, 4 mA output
drive, 3.3 V tolerant
DATA1
38
I/O
data bit 1 input and output
bidirectional pad, push-pull input, 3-state output, 4 mA output
drive, 3.3 V tolerant
DATA2
39
I/O
data bit 2 input and output
bidirectional pad, push-pull input, 3-state output, 4 mA output
drive, 3.3 V tolerant
SAF1760
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 19 June 2012
5 of 110
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