74HC164-Q100; 74HCT164-Q100
8-bit serial-in, parallel-out shift register
Rev. 1 — 16 August 2013
Product data sheet
1. General description
The 74HC164-Q100; 74HCT164-Q100 is an 8-bit serial-in/parallel-out shift register. The
device features two serial data inputs (DSA and DSB), eight parallel data outputs (Q0 to
Q7). Data is entered serially through DSA or DSB and either input can be used as an
active HIGH enable for data entry through the other input. Data is shifted on the
LOW-to-HIGH transitions of the clock (CP) input. A LOW on the master reset input (MR)
clears the register and forces all outputs LOW, independently of other inputs. Inputs
include clamp diodes that enable the use of current limiting resistors to interface inputs to
voltages in excess of V
CC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Input levels:
For 74HC164-Q100: CMOS level
For 74HCT164-Q100: TTL level
Gated serial data inputs
Asynchronous master reset
Complies with JEDEC standard no. 7A
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
NXP Semiconductors
74HC164-Q100; 74HCT164-Q100
8-bit serial-in, parallel-out shift register
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC164D-Q100
74HCT164D-Q100
74HC164PW-Q100
74HCT164PW-Q100
74HC164BQ-Q100
74HCT164BQ-Q100
40 C
to +125
C
DHVQFN14
40 C
to +125
C
TSSOP14
40 C
to +125
C
Name
SO14
Description
plastic small outline package; 14 leads; body
width 3.9 mm
plastic thin shrink small outline package;
14 leads; body width 4.4 mm
Version
SOT108-1
SOT402-1
Type number
plastic dual in-line compatible thermal enhanced SOT762-1
very thin quad flat package; no leads; 14
terminals; body 2.5
3
0.85 mm
4. Functional diagram
SRG8
8
9
1
2
C1/
R
3
4
&
1D
DSA
DSB
3
1
2
4
5
6
10
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
001aac424
5
6
10
11
12
13
CP
MR
8
9
11
12
13
001aac423
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
DSA
DSB
CP
MR
1
2
8
9
3
4
5
6
10
11
12
13
8-BIT SERIAL−IN/PARALLEL−OUT
SHIFT REGISTER
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
001aac425
Fig 3.
Logic diagram
74HC_HCT164_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 16 August 2013
2 of 18
NXP Semiconductors
74HC164-Q100; 74HCT164-Q100
8-bit serial-in, parallel-out shift register
DSA
D
DSB
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CP
FF1
R
D
CP
FF2
R
D
CP
FF3
R
D
CP
FF4
R
D
CP
FF5
R
D
CP
FF6
R
D
CP
FF7
R
D
CP
FF8
R
D
CP
MR
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
001aac616
Fig 4.
Functional diagram
5. Pinning information
5.1 Pinning
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5.
Pin configuration SO14 and TSSOP14
Fig 6.
Pin configuration DHVQFN14
74HC_HCT164_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 16 August 2013
3 of 18
NXP Semiconductors
74HC164-Q100; 74HCT164-Q100
8-bit serial-in, parallel-out shift register
5.2 Pin description
Table 2.
Symbol
DSA
DSB
Q0 to Q7
GND
CP
MR
V
CC
Pin description
Pin
1
2
3, 4, 5, 6, 10, 11, 12, 13
7
8
9
14
Description
data input
data input
output
ground (0 V)
clock input (LOW-to-HIGH, edge-triggered)
master reset input (active LOW)
positive supply voltage
6. Functional description
Table 3.
Operating
modes
Reset (clear)
Shift
Function table
[1]
Input
MR
L
H
H
H
H
[1]
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition
q = lower case letters indicate the state of the referenced input one set-up time prior to the LOW-to-HIGH clock transition
= LOW-to-HIGH clock transition
Output
CP
X
DSA
X
l
l
h
h
DSB
X
l
h
l
h
Q0
L
L
L
L
H
Q1 to Q7
L to L
q0 to q6
q0 to q6
q0 to q6
q0 to q6
74HC_HCT164_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 16 August 2013
4 of 18
NXP Semiconductors
74HC164-Q100; 74HCT164-Q100
8-bit serial-in, parallel-out shift register
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
0.5
V < V
O
< V
CC
+ 0.5 V
[1]
[1]
Min
0.5
-
-
-
-
50
65
[2]
Max
+7
20
20
25
50
-
+150
500
Unit
V
mA
mA
mA
mA
mA
C
mW
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO14 package: P
tot
derates linearly with 8 mW/K above 70
C.
For TSSOP14 packages: P
tot
derates linearly with 5.5 mW/K above 60
C.
For DHVQFN14 packages: P
tot
derates linearly with 4.5 mW/K above 60
C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
V
CC
V
I
V
O
T
amb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
74HC164-Q100
Min
2.0
0
0
40
-
-
-
Typ
5.0
-
-
+25
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
74HCT164-Q100
Min
4.5
0
0
40
-
-
-
Typ
5.0
-
-
+25
-
1.67
-
Max
5.5
V
CC
V
CC
+125
-
139
-
V
V
V
C
ns/V
ns/V
ns/V
Unit
74HC_HCT164_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 16 August 2013
5 of 18
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