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MPC8555EVTAKF

Description
RISC PROCESSOR, PBGA783, 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, FLIP CHIP, PLASTIC, BGA-783
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size1MB,88 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Download Datasheet Parametric View All

MPC8555EVTAKF Overview

RISC PROCESSOR, PBGA783, 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, FLIP CHIP, PLASTIC, BGA-783

MPC8555EVTAKF Parametric

Parameter NameAttribute value
MakerNXP
Parts packaging codeBGA
package instructionBGA,
Contacts783
Reach Compliance Codeunknow
Address bus width15
bit size32
boundary scanYES
External data bus width64
FormatFIXED POINT
Integrated cacheYES
JESD-30 codeS-PBGA-B783
length29 mm
low power modeYES
Number of terminals783
Maximum operating temperature105 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Package shapeSQUARE
Package formGRID ARRAY
Certification statusNot Qualified
Maximum seat height3.75 mm
speed600 MHz
Maximum supply voltage1.26 V
Minimum supply voltage1.14 V
Nominal supply voltage1.2 V
surface mountYES
technologyCMOS
Temperature levelOTHER
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
width29 mm
uPs/uCs/peripheral integrated circuit typeMICROPROCESSOR, RISC
Freescale Semiconductor
Technical Data
MPC8555EEC
Rev. 4.2, 1/2008
MPC8555E PowerQUICC™ III
Integrated Communications Processor
Hardware Specification
The MPC8555E integrates a PowerPC™ processor core
built on Power Architecture™ technology with system logic
required for networking, telecommunications, and wireless
infrastructure applications. The MPC8555E is a member of
the PowerQUICC™ III family of devices that combine
system-level support for industry-standard interfaces with
processors that implement the embedded category of the
Power Architecture technology. For functional
characteristics of the processor, refer to the
MPC8555E
PowerQUICC™ III Integrated Communications Processor
Reference Manual.
To locate any published errata or updates for this document
refer to http://www.freescale.com or contact your Freescale
sales office.
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Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 8
Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 13
Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Ethernet: Three-Speed, MII Management . . . . . . . . . . 22
Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
CPM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . . . 56
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
System Design Information . . . . . . . . . . . . . . . . . . . . . 78
Document Revision History . . . . . . . . . . . . . . . . . . . . 85
Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . 86
© Freescale Semiconductor, Inc., 2008. All rights reserved.
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