MPC8560CPX833LB datasheet, PDF

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MPC8560CPX833LB: Description32-BIT, 883MHz, RISC PROCESSOR, PBGA783, 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，108 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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MPC8560CPX833LB Overview

32-BIT, 883MHz, RISC PROCESSOR, PBGA783, 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783

MPC8560CPX833LB Parametric

Parameter Name	Attribute value
Maker	NXP
Parts packaging code	BGA
package instruction	BGA,
Contacts	783
Reach Compliance Code	unknow
ECCN code	3A001.A.3
Address bus width	64
bit size	32
boundary scan	YES
maximum clock frequency	166 MHz
External data bus width	64
Format	FIXED POINT
Integrated cache	YES
JESD-30 code	S-PBGA-B783
length	29 mm
low power mode	YES
Number of terminals	783
Maximum operating temperature	105 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Certification status	Not Qualified
Maximum seat height	3.75 mm
speed	883 MHz
Maximum supply voltage	1.26 V
Minimum supply voltage	1.14 V
Nominal supply voltage	1.2 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	29 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC

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Freescale Semiconductor

Technical Data

MPC8560EC

Rev. 4.2, 1/2008

MPC8560

Integrated Processor

Hardware Specifications

The MPC8560 integrates a PowerPC™ processor core built

on Power Architecture™ technology with system logic

required for networking, telecommunications, and wireless

infrastructure applications. The MPC8560 is a member of

the PowerQUICC™ III family of devices that combine

system-level support for industry-standard interfaces with

processors that implement the embedded category of the

Power Architecture technology. For functional

characteristics of the processor, refer to the

MPC8560

PowerQUICC III Integrated Communications Processor

Reference Manual.

To locate any published errata or updates for this document,

contact your Freescale sales office.

Contents

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 8

Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 13

Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 17

DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Ethernet: Three-Speed, MII Management . . . . . . . . 23

Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

CPM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

PCI/PCI-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

RapidIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 70

Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

System Design Information . . . . . . . . . . . . . . . . . . . 92

Document Revision History . . . . . . . . . . . . . . . . . . . 99

Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . 104

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