SmartMX2 P40 family
P40C012/040/072
Secure smart card controller
Rev. 3.0 — 24 April 2015
262830
Product short data sheet
COMPANY PUBLIC
1. Introduction
1.1 Product overview
SmartMX2-P40 family is a secure microcontroller family designed and manufactured by
NXP Semiconductors. It is part of the SmartMX2-IC family produced in 90 nm CMOS
technology. SmartMX2-P40 is an ISO/IEC 7816 compliant contact secure microcontroller
platform, built around the proven and powerful MRK3-SC RISC core. The overall
architecture of P40 has been streamlined to meet the performance requirements of
payment and eGovernment contact smart card applications.
NXP‘s SmartMX2 P40 security architecture is built on more than 15 years of experience in
this area. The SmartMX2-P40 product family provides embedded firmware forming a
Hardware Abstraction Layer (HAL). The use of this HAL makes it easier to efficiently
develop embedded software for the device.
SmartMX2-P40 supports DES, AES, ECC, RSA cryptography, hash computation, and
random-number generation. For asymmetric RSA and ECC cryptography, a dedicated
coprocessor supports RSA key lengths up to 4096 bits and ECC key lengths up to
521 bits. Coprocessors for symmetric ciphers support DES (single DES, 2-key 3DES, and
3-key 3DES), plus AES cryptography with bit lengths of 128-bit, 192-bit, or 256-bit. The
memory configuration, which combines up to 265 KB User ROM, 6 KB RAM, up to 72 KB
EEPROM, handles static code and dynamic data separately, and enables fast code
execution from ROM.
The P40 family also provides a ready-to-use crypto library with highly efficient software
APIs for all cryptographic functions (RSA key length up to 2048 bits, ECC up to 384 bits).
Table 1.
Product
type
P40C012
P40C040
P40C072
[1]
Feature table
EEPROM
[KB]
13
40
72
User
ROM
[KB]
[1]
up to 265
up to 265
up to 265
Total
RAM [B]
6144
6144
6144
RAM allocation
CPU/PKCC
dynamic
dynamic
dynamic
Coprocessor
PKC
yes
yes
yes
ISO/IEC 7816 Interface
option
DES AES IO pads
yes
yes
yes
yes
yes
yes
1
1
1
ISO 7816
Refer to
Section 14.3
NXP Semiconductors
P40C012/040/072
Secure smart card controller
2. General description
2.1 General remarks
This document offers an introduction into the features and the architecture of the
SmartMX2 P40 products.
The product data sheet and other detailed documentation, e.g. for Card Operating System
(COS) development are available through NXP’s portal for secured documentation.
Access to such documents is granted on a need-to-know basis. Contact NXP sales for
registration and access.
2.2 Naming conventions
Table 2.
P40xeee
x
Interface and feature configuration identifier, as currently defined, e.g.:
x = C:
eee
Asymmetric and symmetric cryptography implemented, ISO/IEC 7816
contact interface
Naming conventions
Indication of the Non-Volatile memory size in KB
eee = 012: 13 KB EEPROM implemented
eee = 040: 40 KB EEPROM implemented
eee = 072: 72 KB EEPROM implemented
2.3 Contact interfaces
Operating in accordance with ISO/IEC 7816, the SmartMX2 P40 contact interface is
supported by a built-in Universal Asynchronous Receiver/Transmitter (UART). P40 UART
enables data rates of up to 688 kbit/s allowing for the automatic generation of all typical
baud rates and supports transmission protocols T=0 and T=1.
2.4 Public Key Crypto (PKC) coprocessor
The PKCC is speeding up the computation of public-key cryptographic operations within
the P40C012/040/072.
The PKC coprocessor flexible interface provides programmers with the freedom to
implement their own cryptographic algorithms. A Common Criteria certified crypto library
from NXP providing a large range of required functions is available for all devices listed in
Table 4
in order to support customers in implementing public key-based solutions.
2.5 Coprocessor for DES and AES
The DES algorithm, widely used for symmetric encryption, is supported by a dedicated,
high performance, highly attack-resistant hardware coprocessor. Relevant standards
(ISO/IEC, ANSI, FIPS) are fully supported. A secure crypto library element for DES is
available.
The same coprocessor supports secure AES as well. The implementation is based on
FIPS197 as standardized by the National Institute for Standards and Technology (NIST),
for key lengths of 128-bit, 192-bit, and 256-bit with performance levels comparable to
P40C040_C072_SMX2_FAM_SDS
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product short data sheet
COMPANY PUBLIC
Rev. 3.0 — 24 April 2015
262830
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NXP Semiconductors
P40C012/040/072
Secure smart card controller
DES. AES is the next generation for symmetric data encryption and recommended
successor to DES providing significantly improved security level. A secure crypto library
element for AES is available.
2.6 Security features
Advanced 0.09
μm
CMOS technology, with seven metal layers, provides enhanced
protection against reverse engineering and probing attacks, and produces a highly
protective mesh of active and dynamic multi-threaded shielding.
SmartMX2 P40 incorporates a wide range of both inherent and OS-controlled security
features as a countermeasure against all types of attacks. NXP Semiconductors apply
their extensive knowledge of chip security, very dense CMOS technology and active
shielding methodology.
As attacks evolve over time, the multi-dimensional approach of the SmartMX2 P40
security architecture allows for more proactive and continuous enhancements of the
security mechanisms compared to alternative and less versatile approaches. This makes
SmartMX2 P40 a future-proof secure micro-controller platform neutralizing all side
channel and fault attacks as well as reverse engineering efforts.
P40C040_C072_SMX2_FAM_SDS
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product short data sheet
COMPANY PUBLIC
Rev. 3.0 — 24 April 2015
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NXP Semiconductors
P40C012/040/072
Secure smart card controller
3. Features and benefits
3.1 Standard P40C012/040/072 features
EEPROM: 13, 40 or 72 KB
ROM: up to 265 KB
RAM: 6144 B split into area usable for CPU and PKC coprocessor.
Dedicated, RISC based Smart Card CPU
PKC coprocessor
Boolean operations for acceleration of major Public Key Cryptography (PKC)
systems such as RSA and ECC
32-bit operand input/output interface
High speed DES/AES coprocessor
ISO/IEC 7816 contact interface with UART supporting standard protocols T=0 and T=1
as well as high speed personalization up to 688 kbit/s
High speed 8-, 16- or 32-bit CRC engine according to ITU-T polynomial definition
Low power Random Number Generator (RNG) in hardware, AIS-31 compliant once
NXP Crypto Library functions are used
2.7 V to 5.5 V extended operating voltage range for class B and A (depending on
product)
-25 °C to +85 °C ambient temperature
3.2 Security features
Security sensors
Low and high clock frequency sensor
Low and high temperature sensor
Low and high supply voltage sensor
Single Fault Injection (SFI) attack detection
Light sensors (incl. integrated memory light sensor functionality)
Active shielding
10 bytes Unique ID for each die
Clock input filter for protection against spikes
Optional programmable card disable feature
Memory security (encryption and physical measures) for RAM, NV memory and ROM
P40C040_C072_SMX2_FAM_SDS
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product short data sheet
COMPANY PUBLIC
Rev. 3.0 — 24 April 2015
262830
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NXP Semiconductors
P40C012/040/072
Secure smart card controller
4. Applications
Banking
Multi-application cards
ID cards
Health cards
Electronic driving licences
Digital Signature
High-security access management
Other secure micro controller applications
P40C040_C072_SMX2_FAM_SDS
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product short data sheet
COMPANY PUBLIC
Rev. 3.0 — 24 April 2015
262830
5 of 15
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