PowerPC
™
MPC823e
Reference Manual
The Microprocessor for Mobile Computing
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Acknowledgments
The MPC823e Support Team would like to thank the following people for their
contribution to the success of the MPC823e:
Art Miller, CW Clark, Ken Edwards, Kevin Owen, Ray Burgess, Tom Gunter, John Round, Mike Shoemake,
James Wilson, Chris Lines, Ricardo Berger, Yehuda Rudin, Yair Liebman, Udi Barel, the rest of the Israel
design team, Stu Werbner, Tiffany Huling-Broadous, John Dailey, Lan Nguyen, Richard Hendricks,
Darcy Volden, Trish Sierer, Arnaldo Cruz, Danny Nguyen, Myle Buchanan, Joseph Mayfield, Rodolfo Guillen,
the rest of the product/test engineering team, Brian McCalley, Alan Weiss, Steve Rosebaugh, Jasmine Hsiao,
Mike Collier, John Southard, Joseph Lee, Pat Carr, Mark VandenBrink, the rest of the Systems Software team,
Yoichi Kimura, Yuzo Kuramochi, Tanamachi Goro, Fumihiko Kondo, Keiji Momozaki, Jean-Paul Davi,
Per-Eric Josefsson, Rodney Watt, Axel Streicher, Pierre Juste, Gary Segal, Mark DiPerri, Kurt Miller,
Steve Shoap, Rob Wackerman, Rick Heider, Gary Wilson, Thomas Yeh, Bill Durrenberger, Dave Hyder,
the rest of the Field Applications Engineering/Sales support team, Pamela Mitchell, Nina Friedman,
the rest of the Technical Information Center support team, Dan Malek, Jim Belesiu, Clark Liang, Ronny
Svensson, Mark Wagner, Bulent Egilmez, Kurt Fuqua, Robert Applebaum, Nick Vaccaro, Weifu Shi,
Roozbeh Ghorishi, Robert Ritchey, Brad Scott, Dan Malek, the rest of our customers,
the gang at comp.sys.powerpc.tech and linuxppc-embedded, and to many others.
TABLE OF CONTENTS
Paragraph
Number
Title
Section 1
Introduction
1.1
1.2
1.2.1
1.2.2
1.2.3
1.2.4
1.2.4.1
1.2.4.2
1.3
1.4
1.5
1.6
1.7
1.8
Features ................................................................................................1-1
Architecture ...........................................................................................1-6
The Embedded PowerPC Core ..................................................1-8
The System Interface Unit ..........................................................1-8
The Communication Processor Module .....................................1-9
The Video/LCD Controller ........................................................1-10
The Video Controller .....................................................1-10
The LCD Controller .......................................................1-10
The PCMCIA-ATA Controller ..............................................................1-10
Power Management ............................................................................1-11
System Debug Support .......................................................................1-11
Applications .........................................................................................1-11
Differences Between MPC823 (Rev B) and MPC823e .......................1-12
MPC823e Glueless System Design ....................................................1-12
Section 2
External Signals
2.1
The System Bus Signals .......................................................................2-2
Section 3
Memory Map
Section 4
Reset
4.1
4.1.1
4.1.2
4.1.3
4.1.3.1
4.1.3.2
4.1.3.3
4.1.3.4
4.1.3.5
Types of Reset ......................................................................................4-2
Power-On Reset .........................................................................4-2
External Hard Reset ...................................................................4-3
Internal Hard Reset ....................................................................4-3
Loss of Lock ....................................................................4-3
Software Watchdog Reset ..............................................4-3
Checkstop Reset ............................................................4-3
Debug Port Hard Reset ..................................................4-4
JTAG Reset ....................................................................4-4
Page
Number
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TABLE OF CONTENTS (Continued)
Paragraph
Number
4.1.4
4.1.5
4.1.5.1
4.2
4.3
4.3.1
4.3.1.1
4.3.2
Title
Page
Number
External Soft Reset .................................................................... 4-4
Internal Soft Reset ..................................................................... 4-4
Debug Port Soft Reset .................................................... 4-4
Reset Status Register ........................................................................... 4-5
How to Configure Reset ........................................................................ 4-7
Hard Reset ................................................................................. 4-7
Hard Reset Configuration Word ................................... 4-10
Soft Reset ................................................................................ 4-12
Section 5
Clocks and Power Control
5.1
5.2
5.2.1
5.2.2
5.3
5.3.1
5.3.2
5.3.2.1
5.3.3
5.3.4
5.3.4.1
5.3.4.2
5.3.4.3
5.3.4.4
5.3.5
5.3.5.1
5.3.5.2
5.4
5.4.1
5.4.2
5.4.2.1
5.4.2.2
5.5
Features ................................................................................................ 5-1
Register Model ...................................................................................... 5-3
System Clock and Reset Control Register ................................. 5-3
PLL, Low-Power, and Reset Control Register ........................... 5-7
The Clock Module ............................................................................... 5-10
On-Chip Oscillators and External Clock Input .......................... 5-12
System PLL .............................................................................. 5-12
SPLL Stability ............................................................... 5-13
The Low-Power Clock Divider .................................................. 5-14
Internal Clock Signals .............................................................. 5-16
The General System Clocks ......................................... 5-16
The Baud Rate Generator Clock .................................. 5-19
The Synchronization Clocks ......................................... 5-20
The LCD Clocks ........................................................... 5-21
Clock Configuration .................................................................. 5-22
Mode Clock Pins ........................................................... 5-22
The System Phase-Locked Loop Pins ......................... 5-23
Power Control ..................................................................................... 5-24
Power Rails .............................................................................. 5-24
Keep-Alive Power ..................................................................... 5-25
Power Switching Example ............................................ 5-26
Register Lock ................................................................ 5-27
Low-Power Operation ......................................................................... 5-28
Section 6
The PowerPC Core
6.1
6.2
6.2.1
Features ................................................................................................ 6-1
Basic Structure of the Core ................................................................... 6-2
Instruction Flow Within the Core ................................................ 6-2
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MPC823e REFERENCE MANUAL
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TABLE OF CONTENTS (Continued)
Paragraph
Number
6.2.2
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.4.1
6.3.5
6.3.6
6.3.6.1
6.3.7
6.3.7.1
6.3.8
6.4
6.4.1
6.4.1.1
6.4.1.2
6.4.1.2.1
6.4.1.2.2
6.4.1.2.3
6.4.1.3
6.4.1.3.1
6.4.1.3.2
6.5
6.5.1
6.6
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
6.6.6
6.6.7
6.6.8
6.6.9
6.6.10
6.6.11
6.6.12
6.6.13
6.6.13.1
Title
Page
Number
Basic Instruction Pipeline ...........................................................6-4
Sequencer Unit .....................................................................................6-4
Flow Control ...............................................................................6-5
Issuing Instructions .....................................................................6-6
Interrupts ....................................................................................6-7
Implementing the Precise Exception Model ...............................6-8
Restartability After An Interrupt .....................................6-10
Processing an Interrupt ............................................................6-11
Serialization ..............................................................................6-12
Latency .........................................................................6-12
The External Interrupt ...............................................................6-13
Latency .........................................................................6-13
Interrupt Ordering .....................................................................6-14
The Register Unit ................................................................................6-15
Control Registers ......................................................................6-16
Physical Location of Special Registers .........................6-19
PowerPC Standard Control Register Bit Assignment ....6-20
Machine State Register ....................................6-20
The Condition Register ....................................6-22
Fixed-Point Exception Cause Register ............6-23
Initializing the Control Registers ...................................6-24
System Reset Interrupt ....................................6-24
Hard/Soft Reset ................................................6-24
The Fixed-Point Unit ...........................................................................6-24
XER Update In Divide Instructions ...........................................6-24
The Load/Store Unit ............................................................................6-25
Issuing Load/Store Instructions ................................................6-26
Serializing Load/Store Instructions ...........................................6-27
Instructions Issued to the Data Cache .....................................6-27
Issuing Store Instruction Cycles ...............................................6-27
Issuing Nonspeculative Load Instructions ................................6-27
Executing Unaligned Instructions .............................................6-28
Little-Endian Mode Support ......................................................6-29
Atomic Update Primitives .........................................................6-29
Instruction Timing .....................................................................6-30
Stalling Storage Control Instructions ........................................6-30
Accessing Off-Core Special Registers .....................................6-30
Storage Control Instructions .....................................................6-31
Exceptions ................................................................................6-31
DAR, DSISR, and BAR Operation ................................6-31
Section 7
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