NLV14073BCPG datasheet, PDF - EEWORLD Datasheet

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NLV14073BCPG: DescriptionIC 4000/14000/40000 SERIES, TRIPLE 3-INPUT AND GATE, PDIP14, ROHS COMPLIANT, PLASTIC, DIP-14, Gate; Categorylogic logic; File Size171KB，13 Pages; ManufacturerON Semiconductor; Websitehttp://www.onsemi.cn; Environmental Compliance

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NLV14073BCPG Overview

IC 4000/14000/40000 SERIES, TRIPLE 3-INPUT AND GATE, PDIP14, ROHS COMPLIANT, PLASTIC, DIP-14, Gate

NLV14073BCPG Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	ON Semiconductor
Parts packaging code	DIP
package instruction	ROHS COMPLIANT, PLASTIC, DIP-14
Contacts	14
Reach Compliance Code	unknow
series	4000/14000/40000
JESD-30 code	R-PDIP-T14
JESD-609 code	e3
length	18.86 mm
Logic integrated circuit type	AND GATE
Number of functions	3
Number of entries	3
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
propagation delay (tpd)	300 ns
Filter level	AEC-Q100
Maximum seat height	4.69 mm
Maximum supply voltage (Vsup)	18 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin (Sn)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm

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MC14001B Series

B-Suffix Series CMOS Gates

MC14001B, MC14011B, MC14023B,

MC14025B, MC14071B, MC14073B,

MC14081B, MC14082B

The B Series logic gates are constructed with P and N channel

enhancement mode devices in a single monolithic structure

(Complementary MOS). Their primary use is where low power

dissipation and/or high noise immunity is desired.

Features

http://onsemi.com

MARKING

DIAGRAMS

PDIP−14

P SUFFIX

CASE 646

SOIC−14

D SUFFIX

CASE 751A

TSSOP−14

DT SUFFIX

CASE 948G

SOEIAJ−14

F SUFFIX

CASE 965

= Specific Device Code

= Assembly Location

WL, L

= Wafer Lot

YY, Y

= Year

WW, W = Work Week

= Pb−Free Package

G or

(Note: Microdot may be in either location)

MC140xxB

ALYWG

0xxB

ALYWG

140xxBG

AWLYWW

MC140xxBCP

AWLYYWWG

•

Supply Voltage Range = 3.0 Vdc to 18 Vdc

•

All Outputs Buffered

•

Capable of Driving Two Low−power TTL Loads or One Low−power

•

Schottky TTL Load Over the Rated Temperature Range.

Double Diode Protection on All Inputs Except: Triple Diode

Protection on MC14011B and MC14081B

Pin−for−Pin Replacements for Corresponding CD4000 Series

B Suffix Devices

These Devices are Pb−Free and are RoHS Compliant

NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

Parameter

DC Supply Voltage Range

Input or Output Voltage Range

(DC or Transient)

Input or Output Current

(DC or Transient) per Pin

Power Dissipation, per Package

(Note 1)

Ambient Temperature Range

Storage Temperature Range

Lead Temperature

(8−Second Soldering)

ESD Withstand Voltage

Human Body Model

Machine Model

Charged Device Model

Value

−0.5

to +18.0

−0.5

to V

+ 0.5

500

−55

to +125

−65

to +150

260

MAXIMUM RATINGS

(Voltages Referenced to V

)

Symbol

, V

out

, I

out

stg

ESD

Unit

°C

> 3000

> 300

N/A

Device

MC14001B

MC14011B

MC14023B

MC14025B

MC14071B

MC14073B

MC14081B

MC14082B

DEVICE INFORMATION

Description

Quad 2−Input NOR Gate

Quad 2−Input NAND Gate

Triple 3−Input NAND Gate

Triple 3−Input NOR Gate

Quad 2−Input OR Gate

Triple 3−Input AND Gate

Quad 2−Input AND Gate

Dual 4−Input AND Gate

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

1. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high−impedance circuit. For proper operation, V

and V

out

should be constrained

to the range V

or V

out

)

Unused inputs must always be tied to an appropriate logic voltage level

(e.g., either V

or V

). Unused outputs must be left open.

Semiconductor Components Industries, LLC, 2012

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 8 of this data sheet.

September, 2012

−

Rev. 9

Publication Order Number:

MC14001B/D

NLV14073BCPG Related Products

	NLV14073BCPG	NLV14011BCPG	NLV14023BCPG	NLV14081BCPG	NLV14082BCPG	NLV14071BCPG	NLV14025BCPG
Description	IC 4000/14000/40000 SERIES, TRIPLE 3-INPUT AND GATE, PDIP14, ROHS COMPLIANT, PLASTIC, DIP-14, Gate	IC 4000/14000/40000 SERIES, QUAD 2-INPUT NAND GATE, PDIP14, ROHS COMPLIANT, PLASTIC, DIP-14, Gate	4000/14000/40000 SERIES, TRIPLE 3-INPUT NAND GATE, PDIP14, ROHS COMPLIANT, PLASTIC, DIP-14	IC 4000/14000/40000 SERIES, QUAD 2-INPUT AND GATE, PDIP14, ROHS COMPLIANT, PLASTIC, DIP-14, Gate	IC 4000/14000/40000 SERIES, DUAL 4-INPUT AND GATE, PDIP14, ROHS COMPLIANT, PLASTIC, DIP-14, Gate	IC 4000/14000/40000 SERIES, QUAD 2-INPUT OR GATE, PDIP14, ROHS COMPLIANT, PLASTIC, DIP-14, Gate	IC 4000/14000/40000 SERIES, TRIPLE 3-INPUT NOR GATE, PDIP14, ROHS COMPLIANT, PLASTIC, DIP-14, Gate
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to	conform to
Maker	ON Semiconductor	ON Semiconductor	ON Semiconductor	ON Semiconductor	ON Semiconductor	ON Semiconductor	ON Semiconductor
Parts packaging code	DIP	DIP	DIP	DIP	DIP	DIP	DIP
package instruction	ROHS COMPLIANT, PLASTIC, DIP-14	ROHS COMPLIANT, PLASTIC, DIP-14	DIP, DIP14,.3	ROHS COMPLIANT, PLASTIC, DIP-14	ROHS COMPLIANT, PLASTIC, DIP-14	ROHS COMPLIANT, PLASTIC, DIP-14	ROHS COMPLIANT, PLASTIC, DIP-14
Contacts	14	14	14	14	14	14	14
Reach Compliance Code	unknow	unknown	compliant	unknown	unknown	unknown	unknown
series	4000/14000/40000	4000/14000/40000	4000/14000/40000	4000/14000/40000	4000/14000/40000	4000/14000/40000	4000/14000/40000
JESD-30 code	R-PDIP-T14	R-PDIP-T14	R-PDIP-T14	R-PDIP-T14	R-PDIP-T14	R-PDIP-T14	R-PDIP-T14
length	18.86 mm	18.86 mm	18.86 mm	18.86 mm	18.86 mm	18.86 mm	18.86 mm
Logic integrated circuit type	AND GATE	NAND GATE	NAND GATE	AND GATE	AND GATE	OR GATE	NOR GATE
Number of functions	3	4	3	4	2	4	3
Number of entries	3	2	3	2	4	2	3
Number of terminals	14	14	14	14	14	14	14
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	DIP	DIP	DIP	DIP	DIP	DIP	DIP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	IN-LINE	IN-LINE	IN-LINE	IN-LINE	IN-LINE	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
propagation delay (tpd)	300 ns	250 ns	300 ns	300 ns	300 ns	300 ns	300 ns
Filter level	AEC-Q100	AEC-Q100	AEC-Q100	AEC-Q100	AEC-Q100	AEC-Q100	AEC-Q100
Maximum seat height	4.69 mm	4.69 mm	4.69 mm	4.69 mm	4.69 mm	4.69 mm	4.69 mm
Maximum supply voltage (Vsup)	18 V	18 V	18 V	18 V	18 V	18 V	18 V
Minimum supply voltage (Vsup)	3 V	3 V	3 V	3 V	3 V	3 V	3 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	NO	NO	NO	NO	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY
Terminal form	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE
Terminal pitch	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	7.62 mm	7.62 mm	7.62 mm	7.62 mm	7.62 mm	7.62 mm	7.62 mm
JESD-609 code	e3	e3	-	e3	e3	e3	e3
Terminal surface	Tin (Sn)	Tin (Sn)	-	Tin (Sn)	Tin (Sn)	Tin (Sn)	Tin (Sn)

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