HYB18T256161AF-22 datasheet, PDF

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HYB18T256161AF-22: DescriptionDDR DRAM, 16MX16, 0.45ns, CMOS, PBGA84; Categorystorage storage; File Size2MB，90 Pages; ManufacturerQIMONDA; Environmental Compliance

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HYB18T256161AF-22 Overview

DDR DRAM, 16MX16, 0.45ns, CMOS, PBGA84

HYB18T256161AF-22 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	QIMONDA
package instruction	FBGA, BGA84,9X15,32
Reach Compliance Code	unknow
Maximum access time	0.45 ns
Maximum clock frequency (fCLK)	450 MHz
I/O type	COMMON
interleaved burst length	4,8
JESD-30 code	R-PBGA-B84
memory density	268435456 bi
Memory IC Type	DDR DRAM
memory width	16
Number of terminals	84
word count	16777216 words
character code	16000000
Maximum operating temperature	85 °C
Minimum operating temperature
organize	16MX16
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	FBGA
Encapsulate equivalent code	BGA84,9X15,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, FINE PITCH
power supply	2 V
Certification status	Not Qualified
refresh cycle	8192
Continuous burst length	4,8
Maximum standby current	0.004 A
Maximum slew rate	0.19 mA
Nominal supply voltage (Vsup)	2 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM

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Data Sheet, Rev. 1.30, July 2005

HYB18T256161AF–22/25/28/33

HYB18T256161AFL25/28/33

256-Mbit x16 GDDR2 DRAM

RoHS compliant

Memory Products

N e v e r

s t o p

t h i n k i n g .

HYB18T256161AF–[22/25/28/33] L[25/28/33]

256-Mbit DDR2 SGRAM

Table of content

1.1

1.2

1.3

1.4

1.5

1.6

1.7

2.1

2.2

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

2.2.6

2.3

2.3.1

2.4

2.5

2.6

2.6.1

2.6.2

2.6.3

2.6.4

2.6.5

2.6.6

2.7

2.7.1

2.7.2

2.8

2.8.1

2.8.2

2.8.3

2.8.4

2.9

2.9.1

2.9.2

2.10

2.11

2.11.1

2.11.2

2.12

2.13

2.14

5.1

5.2

Overview

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

256Mbit DDR2 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Input/Output Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Functional Description

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Basic Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power On and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Programming the Mode Register and Extended Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . .

DDR2 SDRAM Mode Register Set (MRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DDR2 SDRAM Extended Mode Register Set (EMRS(1)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

EMRS(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

EMRS(3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Off-Chip Driver (OCD) Impedance Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Extended Mode Register Set for OCD impedance adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . .

On-Die Termination (ODT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bank Activate Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Read and Write Commands and Access Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Posted CAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Write Data Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Burst Interruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Precharge Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Read Operation Followed by a Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Write followed by Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Auto-Precharge Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Read with Auto-Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Write with Auto-Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Read or Write to Precharge Command Spacing Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Concurrent Auto-Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Auto-Refresh Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Self-Refresh Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Other Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

No Operation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Deselect Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DLL-off Mode Clock Speed Operation Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Clock Frequency Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Asynchronous CKE Low Reset Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Truth Tables

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Absolute Maximum Ratings

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Electrical Characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

DC & AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Rev. 1.30, 2005-07

11222004-7N66-547B

Data Sheet

HYB18T256161AF-22 Related Products

	HYB18T256161AF-22	HYB18T256161AF-25	HYB18T256161AFL-33
Description	DDR DRAM, 16MX16, 0.45ns, CMOS, PBGA84	DDR DRAM, 16MX16, 0.55ns, CMOS, PBGA84, GREEN, PLASTIC, TFBGA-84	DDR DRAM, 16MX16, 0.6ns, CMOS, PBGA84
Is it Rohs certified?	conform to	conform to	conform to
Maker	QIMONDA	QIMONDA	QIMONDA
package instruction	FBGA, BGA84,9X15,32	TFBGA,	FBGA, BGA84,9X15,32
Reach Compliance Code	unknow	unknown	unknown
Maximum access time	0.45 ns	0.55 ns	0.6 ns
JESD-30 code	R-PBGA-B84	R-PBGA-B84	R-PBGA-B84
memory density	268435456 bi	268435456 bit	268435456 bit
Memory IC Type	DDR DRAM	DDR DRAM	DDR DRAM
memory width	16	16	16
Number of terminals	84	84	84
word count	16777216 words	16777216 words	16777216 words
character code	16000000	16000000	16000000
Maximum operating temperature	85 °C	85 °C	85 °C
organize	16MX16	16MX16	16MX16
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	FBGA	TFBGA	FBGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, FINE PITCH
Certification status	Not Qualified	Not Qualified	Not Qualified
Nominal supply voltage (Vsup)	2 V	2 V	1.8 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	OTHER	OTHER	OTHER
Terminal form	BALL	BALL	BALL
Terminal pitch	0.8 mm	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM
Maximum clock frequency (fCLK)	450 MHz	-	300 MHz
I/O type	COMMON	-	COMMON
interleaved burst length	4,8	-	4,8
Output characteristics	3-STATE	-	3-STATE
Encapsulate equivalent code	BGA84,9X15,32	-	BGA84,9X15,32
power supply	2 V	-	1.8 V
refresh cycle	8192	-	8192
Continuous burst length	4,8	-	4,8
Maximum standby current	0.004 A	-	0.004 A
Maximum slew rate	0.19 mA	-	0.16 mA

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