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ATF20V8B-10SI

Description
High- Performance EE PLD
CategoryProgrammable logic devices    Programmable logic   
File Size524KB,17 Pages
ManufacturerAtmel (Microchip)
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ATF20V8B-10SI Overview

High- Performance EE PLD

ATF20V8B-10SI Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Parts packaging codeSOIC
package instructionSOP, SOP24,.4
Contacts24
Reach Compliance Codeunknow
Other features8 MACROCELLS
ArchitecturePAL-TYPE
maximum clock frequency68 MHz
JESD-30 codeR-PDSO-G24
JESD-609 codee0
length15.4 mm
Humidity sensitivity level2
Dedicated input times12
Number of I/O lines8
Number of entries20
Output times8
Number of product terms64
Number of terminals24
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize12 DEDICATED INPUTS, 8 I/O
Output functionMACROCELL
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP24,.4
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)240
power supply5 V
Programmable logic typeFLASH PLD
propagation delay10 ns
Certification statusNot Qualified
Maximum seat height2.65 mm
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width7.5 mm
Base Number Matches1
Features
Industry Standard Architecture
– Emulates Many 24-Pin PALs
®
– Low Cost Easy-to-Use Software Tools
High-Speed Electrically Erasable Programmable Logic Devices
– 7.5 ns Maximum Pin-to-Pin Delay
Several Power Saving Options
Device
ATF20V8B
ATF20V8BQ
ATF20V8BQL
I
CC
, Stand-By
50 mA
35 mA
5 mA
I
CC
, Active
55 mA
40 mA
20 mA
CMOS and TTL Compatible Inputs and Outputs
Input and I/O Pull-Up Resistors
Advanced Flash Technology
– Reprogrammable
– 100% Tested
High Reliability CMOS Process
– 20 Year Data Retention
– 100 Erase/Write Cycles
– 2,000V ESD Protection
– 200 mA Latchup Immunity
Commercial and Industrial Temperature Ranges
Dual-in-Line and Surface Mount Packages in Standard Pinouts
High-
Performance
EE PLD
ATF20V8B
Block Diagram
Pin Configurations
Pin Name
CLK
I
I/O
OE
*
V
CC
Function
Clock
Logic Inputs
Bidirectional Buffers
Output Enable
No Internal Connection
+5V Supply
CLK/IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GND
1
2
3
4
5
6
7
8
9
10
11
12
TSSOP Top View
24
23
22
21
20
19
18
17
16
15
14
13
VCC
IN
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
OE/IN
DIP/SOIC
PLCC Top View
Rev. 0407E–05/98
1
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