2510CYGLF-T datasheet, PDF - EEWORLD Datasheet

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2510CYGLF-T: DescriptionPLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PDSO24; Categorylogic logic; File Size185KB，7 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/; Environmental Compliance

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2510CYGLF-T Overview

PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PDSO24

2510CYGLF-T Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Renesas Electronics Corporation
package instruction	TSSOP,
Reach Compliance Code	compli
Input adjustment	STANDARD
JESD-30 code	R-PDSO-G24
JESD-609 code	e3
length	7.8 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Number of functions	1
Number of inverted outputs
Number of terminals	24
Actual output times	10
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.15 ns
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.63 V
Minimum supply voltage (Vsup)	2.97 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	4.4 mm

2510CYGLF-T Preview

Integrated

Circuit

Systems, Inc.

ICS2510C

3.3V Phase-Lock Loop Clock Driver

General Description

The ICS2510C

is a high performance, low skew, low jitter

clock driver. It uses a phase lock loop (PLL) technology to

align, in both phase and frequency, the CLKIN signal with

the CLKOUT signal. It is specifically designed for use with

synchronous SDRAMs. The

ICS2510C

operates at 3.3V VCC

and drives up to ten clock loads.

One bank of ten outputs provide low-skew, low-jitter copies

of CLKIN. Output signal duty cycles are adjusted to 50

percent, independent of the duty cycle at CLKIN. Outputs

can be enabled or disabled via control (OE) inputs. When the

OE inputs are high, the outputs align in phase and frequency

with CLKIN; when the OE inputs are low, the outputs are

disabled to the logic low state.

The

ICS2510C

does not require external RC filter

components. The loop filter for the PLL is included on-chip,

minimizing component count, board space, and cost. The test

mode shuts off the PLL and connects the input directly to the

output buffer. This test mode, the

ICS2510C

can be use as

low skew fanout clock buffer device. The

ICS2510C

comes

in 24 pin 173mil Thin Shrink Small-Outline package (TSSOP)

package.

Features

•

Meets or exceeds PC133 registered DIMM

specification1.1

Spread Spectrum Clock Compatible

Distributes one clock input to one bank of ten outputs

Operating frequency 25MHz to 175MHz

External feedback input (FBIN) terminal is used to

synchrionize the outputs to the clock input

No external RC network required

Operates at 3.3V Vcc

Plastic 24-pin 173mil TSSOP package

Block Diagram

FBOUT

CLK0

CLK1

CLK2

FBIN

CLKIN

PLL

CLK3

CLK4

AVCC

CLK5

CLK6

CLK7

CLK8

CLK9

Pin Configuration

AGND

VCC

CLK0

CLK1

CLK2

GND

CLK3

CLK4

VCC

FBOUT

CLKIN

AVCC

VCC

CLK9

CLK8

GND

CLK7

CLK6

CLK5

VCC

FBIN

24 Pin TSSOP

2510 C Rev C 11/01/00

ICS reserves the right to make changes in the device data identified in

this publication without further notice. ICS advises its customers to

obtain the latest version of all device data to verify that any

information being relied upon by the customer is current and accurate.

ICS2510C

ICS2510C

Pin Descriptions

PIN NUMBER

2, 10, 14

6, 7, 18, 19

PIN NAME

AGND

VCC

CLK0

CLK1

CLK2

GND

CLK3

CLK4

FBOUT

FBIN

CLK5

CLK6

CLK7

CLK8

CLK9

VCC

AVCC

CLKIN

TYPE

PWR

OUT

PWR

OUT

PWR

DESCRIPTION

Analog Ground

Power Supply (3.3V)

Buffered clock output.

Ground

Buffered clock output.

Output enable (has internal pull_up). When high, normal operation.

When low, clock outputs are disabled to a logic low state.

Feedback output

Feedback input

Buffered clock output.

Power Supply (3.3V) digital supply.

Analog power supply (3.3V). When input is ground PLL is off and

bypassed.

Clock input

Note:

1. Weak pull-ups on these inputs

Functionality

INPUTS

AVCC

3.33

CLK (9:0)

Driven

OUTPUTS

FBOUT

Driven

Source

PLL

CLKIN

PLL

Shutdown

Test mode:

When AVCC is 0, shuts off the PLL

and connects the input directly to the output buffers

Buffer Mode

Driven

ICS2510C

Absolute Maximum Ratings

Supply Voltage (AVCC) . . . . . . . . . . . . . . . . . . .

Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . .

Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ambient Operating Temperature . . . . . . . . . . . .

Storage Temperature . . . . . . . . . . . . . . . . . . . . . .

AVCC < (V

+ 0.7V)

4.3 V

GND –0.5 V to V

+0.5 V

0°C to +70°C

–65°C to +150°C

Stresses above those listed under

Absolute Maximum Ratings

may cause permanent damage to the device. These ratings are

stress specifications only and functional operation of the device at these or any other conditions above those listed in the

operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended

periods may affect product reliability.

Electrical Characteristics - OUTPUT

= 0 - 70C; V

= V

DDL

= 3.3 V +/-10%; C

= 20 - 30 pF; RL = 470 Ohms (unless otherwise stated)

= V

*(0.5)

= V

*(0.5)

= 8 mA

= 0.8 V, V

= 2.0 V

= 2.0 V, V

= 08 V

= 1.5V;Cl=30pF

= Vdd/2; Fout<66.6MHz

at 66MHz - 100MHz ; loaded Outputs

at 133MHz ; loaded Outputs

10000 cycles; Cl=30pF

= 1.5 V (Window) Output to Output

= Vdd/2; CLKIN-FBIN

= Vdd/2; CLKIN-FBIN;

Phase error -Jitter

pe3

Delay Jitter @ 133MHz

= 1.5 V; PLL_EN = 0

Delay Input-Output

Guaranteed by design, not 100% tested in production.

PARAMETER

Output Impedance

Output High Voltage

Output Low Voltage

Rise Time

Fall Time

Duty Cycle

Cycle to Cycle jitter

Absolute Jitter

Skew

Phase error

SYMBOL

DSP

DSN

Tcyc-cyc

Tjabs

CONDITIONS

MIN

TYP

2.9

0.25

1.4

1.5

3.3

MAX UNITS

Ω

0.4

2.1

2.7

100

150

3.7

2.4

0.5

-150

-50

ICS2510C

Electrical Characteristics - Input & Supply

= 0 - 70C; Supply Voltage V

= 3.3 V +/-10% (unless otherwise stated)

PARAMETER

SYMBOL

CONDITIONS

Input High Voltage

Input Low Voltage

Input High Current

= V

Input Low Current

= 0 V;

= 0 pF; F

@ 66M

Operating current

DD1

Input Capacitance

Logic Inputs

Output Capacitance

Logic Outputs

MIN

-0.3

TYP

0.1

140

MAX UNITS

+0.3

0.8

100

170

Guarenteed by design, not 100% tested in production.

Timing requirements over recommended ranges of supply

voltage and operating free-air temperature

Symbol

Fclk

Parameter

Input clock frequency

Test Conditions

Min.

Max.

175

Unit

MHz

Input clock frequency

duty cycle

Stabilization time

After power up

Note: Time required for the PLL circuit to obtain phase lock of its feedback signal to its reference

In order for phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be

Until phase lock is obtained, the specifications for parameters given in the switching characteristics table are not

ICS2510C

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

30 pF

500

Ω

Figure 1. Load Circuit for Outputs

Notes:

Figure 2. Voltage Waveforms

1. C

includes probe and jig capacitance.

Propagation Delay Times

2. All input pulses are supplied by generators having the following

characteristics:

PRR

133 MHz, Z

= 5 0

1.2 ns, T

1.2 ns.

3. The outputs are measured one at a time with one transition per measurement.

Figure 3. Phase Error and Skew Calculations

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2510CYGLF-T Related Products

	2510CYGLF-T	2510CYG-T
Description	PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PDSO24	PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PDSO24
Is it Rohs certified?	conform to	incompatible
Maker	Renesas Electronics Corporation	Renesas Electronics Corporation
package instruction	TSSOP,	TSSOP,
Reach Compliance Code	compli	compliant
Input adjustment	STANDARD	STANDARD
JESD-30 code	R-PDSO-G24	R-PDSO-G24
JESD-609 code	e3	e0
length	7.8 mm	7.8 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
Number of functions	1	1
Number of terminals	24	24
Actual output times	10	10
Maximum operating temperature	70 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	TSSOP
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260	240
Certification status	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.15 ns	0.15 ns
Maximum seat height	1.2 mm	1.2 mm
Maximum supply voltage (Vsup)	3.63 V	3.63 V
Minimum supply voltage (Vsup)	2.97 V	2.97 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V
surface mount	YES	YES
Temperature level	COMMERCIAL	COMMERCIAL
Terminal surface	Matte Tin (Sn)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	30	30
width	4.4 mm	4.4 mm

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