Single Event Radiation Hardened High Speed, Current
Mode PWM
IS-1845ASRH, IS-1845ASEH
The IS-1845ASRH, IS-1845ASEH are
designed to be used in switching
power supplies operating in current-
mode. The rising edge of the on-chip
oscillator turns on the output. Turn-off
is controlled by the current sense comparator and occurs when
the sensed current reaches a peak controlled by the error
amplifier.
TM
NOT RECOM
MENDED FO
R NEW DESIG
R E C O MME N
NS
DED REPLA
CEMENT PA
ISL7884XAR
RT
H, ISL7884X
AEH
Features
• Electrically Screened to DSCC SMD #
5962-01509
• QML Qualified per MIL-PRF-38535 Requirements
• Radiation Environment
- High Dose Rate. . . . . . . . . . . . . . . . . . . . .300 krad(SI) (Max)
- Low Dose Rate . . . . . . . . . . . . . . . . . . . . . . 50 krad(SI) (Max)
- SEL Immune . . . . . . . . . . . . . . . . . . . . Dielectrically Isolated
- SEU Immune. . . . . . . . . . . . . . . . . . . . . . . . 35MeV/mg/cm
2
- SEU Cross-Section at 89MeV/mg/cm
2
. . . . . . 5 x 10
-6
cm
2
• Low Start-up Current . . . . . . . . . . . . . . . . . . . . . . . 100µA (Typ)
• Fast Propagation Delay . . . . . . . . . . . . . . . . . . . . . . . 80ns (Typ)
• Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . 12V to 20V
• High Output Drive. . . . . . . . . . . . . . . . . . . . . . . . 1A (Peak, Typ)
• Undervoltage Lockout . . . . . 8.8V Start (Typ), 8.2V Stop (Typ)
Constructed with Intersil’s Rad Hard Silicon Gate (RSG)
dielectrically isolated BiCMOS process, these devices are
immune to single event latch-up and have been specifically
designed to provide a high level of immunity to single event
transients. All specified parameters are guaranteed and tested
for 300krad(Si) total dose performance at a high dose rate and
50krad(Si) total dose at a low dose rate.
Detailed Electrical Specifications for these devices are
contained in the SMD
5962-01509.
A “hot-link” is also
provided on our website for downloading the SMD.
Applications
• Current-Mode Switching Power Supplies
• Control of High Current FET Drivers
• Motor Speed and Direction Control
Pin Configurations
IS7-1845ASRH, IS7-1845ASEH
(8 LD CDIP2-T8 SBDIP)
TOP VIEW
COMP
VFB
ISENSE
RTCT
1
2
3
4
8
7
6
5
VREF
VCC
OUT
GND
NC
COMP
VFB
NC
NC
NC
ISENSE
RTCT
NC
IS9-1845ASRH, IS9-1845ASEH
(18 LD FLATPACK)
TOP VIEW
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
NC
VREF
VCC
VC
OUT
NC
GND
OSCGND
NC
NOTES:
1. Grounding the COMP pin does not inhibit the output. The output may be inhibited by applying >1.2V to the ISENSE pin.
2. This part should be operated with C
t
= 3.3nF and R
t
= 10k timing components only.
July 13, 2012
FN9001.5
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Copyright Intersil Americas Inc. 2003, 2008, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
IS-1845ASRH, IS-1845ASEH
Die Characteristics
DIE DIMENSIONS
3090µm x 4080µm (121.6 mils x 159.0 mils)
Thickness: 483µm ± 25.4µm (19 mils ± 1 mil)
Substrate
Radiation Hardened Silicon Gate,
Dielectric Isolation
Backside Finish
Silicon
INTERFACE MATERIALS
Glassivation
Type: Phosphorus Silicon Glass (PSG)
Thickness: 8.0kA ± 1.0kA
Top Metallization
Type: AlSiCu
Thickness: 16.0kA ± 2kA
ASSEMBLY RELATED INFORMATION
Substrate Potential
Unbiased (DI)
ADDITIONAL INFORMATION
Worst Case Current Density
<2.0 x 10
5
A/cm
2
Transistor Count
582
Metallization Mask Layout
IS-1845ASRH
ISENSE
VFB
COMP
RTCT
OSCGND
VREF
GND
GND
OUT
NOTES:
3. Both the GND pads must be bonded to ground.
4. The OUT double-sized bond pad must be double bonded for current sharing purposes.
VC
VCC
5. The OSCGND double-sized bond pad must be double bonded to ground for current sharing purposes.
For additional products, see
www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at
www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see
www.intersil.com
3
FN9001.5
July 13, 2012
MCU
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