85105AGILFT datasheet, PDF - EEWORLD Datasheet

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85105AGILFT: DescriptionLow Skew Clock Driver, 85105 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20; Categorylogic logic; File Size381KB，18 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/; Environmental Compliance

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85105AGILFT Overview

Low Skew Clock Driver, 85105 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20

85105AGILFT Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Renesas Electronics Corporation
package instruction	TSSOP, TSSOP20,.25
Reach Compliance Code	compli
series	85105
Input adjustment	DIFFERENTIAL MUX
JESD-30 code	R-PDSO-G20
JESD-609 code	e3
length	6.5 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER
Humidity sensitivity level	1
Number of functions	1
Number of inverted outputs
Number of terminals	20
Actual output times	4
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP20,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Prop。Delay @ Nom-Su	3.2 ns
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.63 V
Minimum supply voltage (Vsup)	2.97 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	4.4 mm

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Low Skew, 1-to-5, Differential/LVCMOS-to-

0.7V HCSL Fanout Buffer

Data Sheet

85105I

ENERAL

ESCRIPTION

The 85105I is a low skew, high performance 1-to-5 Differential-to-

0.7V HCSL Fanout Buffer. The 85105I has two selectable clock

inputs. The CLK0, nCLK0 pair can accept most standard differential

input levels. The single-ended CLK1 can accept LVCMOS or LVTTL

input levels. The clock enable is internally synchronized to eliminate

runt clock pulses on the outputs during asynchronous assertion/

deassertion of the clock enable pin.

Guaranteed output and par t-to-par t skew characteristics

make the 85105I ideal for those applications demanding well

deﬁned performance and repeatability.

EATURES

•

Five 0.7V differential HCSL outputs

•

Selectable differential CLK0, nCLK0 or LVCMOS inputs

•

CLK0, nCLK0 pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, HCSL

•

CLK1 can accept the following input levels:

LVCMOS or LVTTL

•

Maximum output frequency: 500MHz

•

Translates any single-ended input signal to 3.3V

HCSL levels with resistor bias on nCLK input

•

Output skew: 100ps (maximum)

•

Part-to-part skew: 600ps (maximum)

•

Propagation delay: 3.2ns (maximuml)

•

Additive phase jitter, RMS: 0.24ps (typical)

•

3.3V operating supply

•

-40°C to 85°C ambient operating temperature

•

Available in lead-free (RoHS 6) package

LOCK

IAGRAM

CLK_EN

Pullup

CLK0

Pulldown

nCLK0

Pullup/Pulldown

CLK1

Pulldown

CLK_SEL

Pulldown

nQ0

nQ1

nQ2

IREF

nQ3

nQ4

SSIGNMENT

85105I

20-Lead TSSOP

6.5mm x 4.4mm x 0.925mm Package Body

G Package

Top View

Revision A January 20, 2016

85105AGILFT Related Products

	85105AGILFT	85105AGILF
Description	Low Skew Clock Driver, 85105 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20	Low Skew Clock Driver, 85105 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20
Is it Rohs certified?	conform to	conform to
Maker	Renesas Electronics Corporation	Renesas Electronics Corporation
package instruction	TSSOP, TSSOP20,.25	TSSOP, TSSOP20,.25
Reach Compliance Code	compli	compli
series	85105	85105
Input adjustment	DIFFERENTIAL MUX	DIFFERENTIAL MUX
JESD-30 code	R-PDSO-G20	R-PDSO-G20
JESD-609 code	e3	e3
length	6.5 mm	6.5 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER
Humidity sensitivity level	1	1
Number of functions	1	1
Number of terminals	20	20
Actual output times	4	4
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	TSSOP
Encapsulate equivalent code	TSSOP20,.25	TSSOP20,.25
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260	260
power supply	3.3 V	3.3 V
Prop。Delay @ Nom-Su	3.2 ns	3.2 ns
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm
Maximum supply voltage (Vsup)	3.63 V	3.63 V
Minimum supply voltage (Vsup)	2.97 V	2.97 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V
surface mount	YES	YES
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed
Terminal form	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	30	NOT SPECIFIED
width	4.4 mm	4.4 mm

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