Low Skew, 1-to-2, Differential-to-2.5V, 3.3V
LVPECL/ECL Fanout Buffer
ICS853S011CI
DATA SHEET
General Description
The ICS853S011CI is a low skew, high performance 1-to-2
Differential-to-2.5V/3.3V LVPECL/ECL Fanout Buffer. The
ICS853S011CI is characterized to operate from either a 2.5V or a
3.3V power supply. Guaranteed output and part-to-part skew
characteristics make the ICS853S011CI ideal for those clock
distribution applications demanding well defined performance and
repeatability.
Features
•
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Two differential 2.5V, 3.3V LVPECL/ECL outputs
One differential PCLK, nPCLK input pair
PCLK, nPCLK pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
Maximum output frequency: >2.5GHz
Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on nPCLK input
Output skew: 20ps (maximum)
Part-to-part skew: 150ps (maximum)
Propagation delay: 330ps (maximum)
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.8V, V
EE
= 0V
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -3.8V to -2.375V
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
Block Diagram
PCLK
Pulldown
nPCLK
Pullup/Pulldown
Pin Assignment
Q0
nQ0
Q1
nQ1
Q0
nQ0
Q1
nQ1
1
2
3
4
8
7
6
5
V
CC
PCLK
nPCLK
V
EE
ICS853S011CI
8-Lead SOIC, 150MIL
3.90mm x 4.90mm x 1.37
mm package body
M Package
Top View
8-Lead TSSOP, 118MIL
3.0mm x 3.0mm x 0.97
mm package body
G Package
Top View
ICS853S011CGI REVISION A JULY 16, 2013
1
©2013 Integrated Device Technology, Inc.
ICS853S011CI Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1, 2
3, 4
5
6
7
8
Name
Q0, nQ0
Q1, nQ1
V
EE
nPCLK
PCLK
V
CC
Output
Output
Power
Input
Input
Power
Pullup/
Pulldown
Pulldown
Type
Description
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Negative supply pin.
Inverting differential LVPECL clock input. When left floating, defaults to
2
/
3
V
CC
.
Non-inverting differential LVPECL clock input.
Positive supply pin.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
R
PULLDOWN
R
PULLUP
Parameter
Input Pulldown Resistor
Pullup Resistors
Test Conditions
Minimum
Typical
75
37
Maximum
Units
k
k
ICS853S011CGI REVISION A JULY 16, 2013
2
©2013 Integrated Device Technology, Inc.
ICS853S011CI Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Negative Supply Voltage, V
EE
Inputs, V
I
(LVPECL mode)
Inputs, V
I
(ECL mode)
Outputs, I
O
Continuos Current
Surge Current
Operating Temperature Range, T
A
Package Thermal Impedance,
JA
(Junction-to-Ambient) for 8 Lead SOIC
Package Thermal Impedance,
JA
(Junction-to-Ambient) for 8 Lead TSSOP
Storage Temperature, T
STG
Rating
4.6V (LVPECL mode, V
EE
= 0V)
-4.6V (ECL mode, V
CC
= 0V)
-0.5V to V
CC
+ 0.5V
0.5V to V
EE
– 0.5V
50mA
100mA
-40C to +85C
102C/W (0 mps)
145.4C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
CC
= 2.375V to 3.8V; V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
3.3
Maximum
3.8
24
Units
V
mA
Table 3B. LVPECL DC Characteristics,
V
CC
= 3.3V; V
EE
= 0V, T
A
= -40°C to 85°C
-40°C
Symbol
V
OH
V
OL
V
PP
V
CMR
I
IH
I
IL
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Input Voltage;
NOTE 2
Input High Voltage Common
Mode Range; NOTE 2, 3
Input
High Current
Input
Low Current
PCLK, nPCLK
PCLK
nPCLK
-10
-200
Min
2.2575
1.405
150
1.2
Typ
2.36
1.54
800
Max
2.4625
1.6775
1200
3.3
200
-10
-200
Min
2.2275
1.3725
150
1.2
25°C
Typ
2.33
1.51
800
Max
2.4325
1.6475
1200
3.3
200
-10
-200
Min
2.2075
1.3625
150
1.2
85°C
Typ
2.31
1.50
800
Max
2.4125
1.6375
1200
3.3
200
Units
V
V
mV
V
µA
µA
µA
NOTE: Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50
to V
CC
– 2V.
NOTE 2: V
IL
should not be less than -0.3V.
NOTE 3: Common mode voltage is defined as V
IH
.
ICS853S011CGI REVISION A JULY 16, 2013
3
©2013 Integrated Device Technology, Inc.
ICS853S011CI Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Table 3C. LVPECL DC Characteristics,
V
CC
= 2.5V; V
EE
= 0V, T
A
= -40°C to 85°C
-40°C
Symbol
V
OH
V
OL
V
PP
V
CMR
I
IH
I
IL
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Input Voltage;
NOTE 2
Input High Voltage Common
Mode Range; NOTE 2, 3
Input
High Current
Input
Low Current
PCLK, nPCLK
PCLK
nPCLK
-10
-200
Min
1.4675
0.6265
150
1.2
Typ
1.57
0.76
800
Max
1.6725
0.9015
1200
2.5
200
-10
-200
Min
1.4475
0.6125
150
1.2
25°C
Typ
1.55
0.75
800
Max
1.6525
0.8875
1200
2.5
200
-10
-200
Min
1.4375
0.6025
150
1.2
85°C
Typ
1.54
0.74
800
Max
1.6425
0.8775
1200
2.5
200
Units
V
V
mV
V
µA
µA
µA
NOTE: Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50
to V
CC
– 2V.
NOTE 2: V
IL
should not be less than -0.3V.
NOTE 3: Common mode voltage is defined as V
IH
.
Table 3D. ECL DC Characteristics,
V
CC
= 0V; V
EE
= -3.8V to -2.375V, T
A
= -40°C to 85°C
-40°C
Symbol Parameter
V
OH
V
OL
V
PP
V
CMR
I
IH
I
IL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Input Voltage;
NOTE 2
Input High Voltage Common
Mode Range; NOTE 2, 3
Input
High Current
Input
Low Current
PCLK,
nPCLK
PCLK
nPCLK
-10
-200
Min
-1.0425
-1.8975
150
V
EE
+1.2
Typ
-0.94
-1.76
800
Max
-0.8375
-1.6225
1200
0
200
-10
-200
Min
-1.0725
-1.9275
150
V
EE
+1.2
25°C
Typ
-0.8675
-1.79
800
Max
-0.97
-1.6525
1200
0
200
-10
-200
Min
-1.0925
-1.9375
150
V
EE
+1.2
85°C
Typ
-0.8875
-1.80
800
Max
-0.99
-1.6625
1200
0
200
Units
V
V
mV
V
µA
µA
µA
NOTE: Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50
to V
CC
– 2V.
NOTE 2: V
IL
should not be less than -0.3V.
NOTE 3: Common mode voltage is defined as V
IH
.
ICS853S011CGI REVISION A JULY 16, 2013
4
©2013 Integrated Device Technology, Inc.
ICS853S011CI Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
AC Electrical Characteristics
Table 4. AC Characteristics,
V
CC
= -3.8V to -2.375V or , V
CC
= 2.375V to 3.8V; V
EE
= 0V,
T
A
= -40°C to 85°C
-40°C
Symbol
f
MAX
t
PD
tsk(o)
tsk(pp)
tjit
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
Output
Rise/Fall Time
20% to 80%
50
48
0.035
170
Min
Typ
Max
>2.5
320
20
150
0.035
180
Min
25°C
Typ
Max
>2.5
330
20
150
0.035
190
Min
85°C
Typ
Max
>2.5
345
20
150
Units
GHz
ps
ps
ps
ps
t
R
/ t
F
odc
200
52
50
48
200
52
50
48
200
52
ps
%
Output Duty Cycle
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters are measured at f
1.4GHz, unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
ICS853S011CGI REVISION A JULY 16, 2013
5
©2013 Integrated Device Technology, Inc.
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