8SLVD1204NLGI/W datasheet, PDF

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8SLVD1204NLGI/W: DescriptionLow Skew Clock Driver, 8SLVD Series, 8 True Output(s), 0 Inverted Output(s), CMOS; Categorylogic logic; File Size734KB，19 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/; Environmental Compliance

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8SLVD1204NLGI/W Overview

Low Skew Clock Driver, 8SLVD Series, 8 True Output(s), 0 Inverted Output(s), CMOS

8SLVD1204NLGI/W Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Renesas Electronics Corporation
package instruction	HQCCN,
Reach Compliance Code	compli
Other features	SEATED HT CALCULATED
series	8SLVD
Input adjustment	DIFFERENTIAL MUX
JESD-30 code	S-XQCC-N16
JESD-609 code	e3
length	3 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER
Humidity sensitivity level	3
Number of functions	1
Number of inverted outputs
Number of terminals	16
Actual output times	8
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	UNSPECIFIED
encapsulated code	HQCCN
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG
Peak Reflow Temperature (Celsius)	260
propagation delay (tpd)	0.3 ns
Same Edge Skew-Max（tskwd）	0.02 ns
Maximum seat height	1.05 mm
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	3 mm

8SLVD1204NLGI/W Preview

2:4, LVDS Output Fanout Buffer, 2.5V

8SLVD1204

Datasheet

Description

The 8SLVD1204 is a high-performance differential LVDS fanout

buffer. The device is designed for the fanout of high-frequency, very

low additive phase-noise clock and data signals. The 8SLVD1204 is

characterized to operate from a 2.5V power supply. Guaranteed

output-to-output and part-to-part skew characteristics make the

8SLVD1204 ideal for those clock distribution applications demanding

well-defined performance and repeatability.

Two selectable differential inputs and four low skew outputs are

available. The integrated bias voltage reference enables easy

interfacing of single-ended signals to the device inputs. The device is

optimized for low power consumption and low additive phase noise.

Features

•

Four low skew, low additive jitter LVDS output pairs

Two selectable differential clock input pairs

Differential PCLK, nPCLK pairs can accept the following

differential input levels: LVDS, LVPECL

Maximum input clock frequency: 2GHz

LVCMOS/LVTTL interface levels for the control input select pin

Output skew: 20ps (maximum)

Propagation delay: 300ps (maximum)

Low additive phase jitter, RMS; f

REF

= 156.25MHz, V

= 1V,

10kHz - 20MHz: 95fs (maximum)

Full 2.5V supply voltage

Lead-free (RoHS 6), 16-Lead VFQFPN packaging

Supports case temperature ≤ 105°C operations

-40°C to 85°C ambient operating temperature

Block Diagram

VDD

Pin Assignment

nQ1

nQ0

PCLK0

nPCLK0

Pulldown

Pullup/Pulldown

nQ0

12 11 10

Q2 13

nQ2 14

Q3 15

nQ3 16

GND

REF

7 nPCLK0

6 PCLK0

GND GND

VDD

SEL

nQ1

8SLVD1204

PCLK1

nPCLK1

Pulldown

Pullup/Pulldown

nQ2

16 lead VFQFPN

3.0mm x 3.0mm x 0.9mm package body

1.7mm x 1.7mm ePad

NL Package

Top View

GND GND

VDD

nQ3

SEL

Pullup/Pulldown

GND

REF

Reference

Voltage

Generator

8SLVD1204 May 8, 2020

nPCLK1

PCLK1

8SLVD1204 DATASHEET

Pin Description and Pin Characteristic Tables

Table 1. Pin Descriptions

Number

9, 10

11, 12

13, 14

15, 16

Name

GND

SEL

PCLK1

nPCLK1

PCLK0

nPCLK0

REF

Q0, nQ0

Q1, nQ1

Q2, nQ2

Q3, nQ3

Power

Input

Power

Input

Output

Pulldown

Pullup/

Pulldown

Pullup/

Pulldown

Pullup/

Pulldown

Type

Description

Power supply ground.

Reference select control pin. See Table 3 for function. LVCMOS/LVTTL

interface levels.

Non-inverting differential clock/data input.

Inverting differential clock/data input. V

/2 default when left floating.

Power supply pin.

Non-inverting differential clock/data input.

Inverting differential clock/data input. V

/2 default when left floating.

Bias voltage reference for the PCLK, nPCLK inputs.

Differential output pair 0. LVDS interface levels.

Differential output pair 1. LVDS interface levels.

Differential output pair 2. LVDS interface levels.

Differential output pair 3. LVDS interface levels.

NOTE:

Pulldown

and

Pullup

refer to internal input resistors. See Table 2,

Pin Characteristics,

for typical values.

Table 2. Pin Characteristics

Symbol

PULLDOWN

PULLUP

Parameter

Input Capacitance

Input Pulldown Resistor

Input Pullup Resistor

Test Conditions

Minimum

Typical

Maximum

Units

k

Function Table

Table 3. SEL Input Selection Function Table

Input

SEL

Open (default)

Operation

PCLK0, nPCLK0 is the selected differential clock input.

PCLK1, nPCLK1 is the selected differential clock input.

Input buffers are disabled and outputs are static.

NOTE: SEL is an asynchronous control.

8SLVD1204 May 8, 2020

8SLVD1204 DATASHEET

Absolute Maximum Ratings

Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Stresses beyond those listed under

Absolute Maximum Ratings

may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of

product at these conditions or any conditions beyond those listed in the

DC Characteristics or AC Characteristics

is not implied.

Item

Supply Voltage, V

Inputs, V

Outputs, I

Continuous Current

Surge Current

REF

current Sink/Source, I

REF

Maximum Junction Temperature, T

J,MAX

Storage Temperature, T

STG

ESD - Human Body Model, NOTE 1

ESD - Charged Device Model, NOTE 1

NOTE 1: According to JEDEC/JESD JS-001-2012/22-C101E.

Rating

4.6V

-0.5V to V

+ 0.5V

10mA

15mA

±2mA

150°C

-65C to 150C

2000V

1500V

Recommended Operating Conditions

Symbol

Parameter

Ambient air temperature

Junction temperature

Minimum

-40

Typical

Maximum

125

Units

C

NOTE 1: It is the user’s responsibility to ensure that device junction temperature remains below the maximum allowed.

NOTE 2: All conditions in the table must be met to guarantee device functionality.

NOTE 3: The device is verified to the maximum operating junction temperature through simulation.

Electrical Characteristics

Table 4A. Power Supply Characteristics,

= 2.5V ± 5%, T

= -40°C to 85°C

Symbol

Parameter

Power Supply Voltage

SEL = 0 or 1; f

REF

= 100MHz;

Q0 to Q3 terminated 100 between nQx, Qx

Power Supply Current

SEL = 0 or 1; f

REF

= 800MHz;

Q0 to Q3 terminated 100 between nQx, Qx

SEL = 0 or 1; f

REF

= 2GHz;

Q0 to Q3 terminated 100 between nQx, Qx

Test Conditions

Minimum

2.375

Typical

2.5

Maximum

2.625

100

Units

8SLVD1204 May 8, 2020

8SLVD1204 DATASHEET

Table 4B. LVCMOS/LVTTL DC Characteristics,

= 2.5V ± 5%, T

= -40°C to 85°C

Symbol

dI3

Parameter

Open-Pin Voltage

(Default State)

Input High Voltage

Input Low Voltage

Input High Current

Input Low Current

SEL

= V

= 2.625V

= 2.625V, V

= 0V

-150

Test Conditions

Open

0.7 * V

-0.3

Minimum

Typical

/ 2

+ 0.3

0.2 * V

150

Maximum

Units

µA

Table 4C. Differential Input DC Characteristics,

= 2.5V ± 5%, T

= -40°C to 85°C

Symbol

Parameter

Input High

Current

Input Low

Current

PCLK0, nPCLK1

PCLK1, nPCLK1

PCLK0, PCLK1

nPCLK0,

nPCLK1

Test Conditions

= V

= 2.625V

= 2.625V, V

= 0V

= 2.625V, V

= 0V

REF

= ±1mA

REF

< 1.5 GHz

REF

> 1.5 GHz

-10

-150

– 1.50

0.1

0.2

1.0

– 1.35

– 1.15

1.5

– 0.6

Minimum

Typical

Maximum

150

Units

µA

REF

CMR

Reference Voltage for Input Bias

Peak-to-Peak Voltage; NOTE 1

Common Mode Input Voltage;

NOTE 1, 2

NOTE 1: V

should not be less than -0.3V.

NOTE 2: Common mode input voltage is defined at the crosspoint.

Table 4D. LVDS DC Characteristics,

= 2.5V ± 5%, T

= -40°C to 85°

Symbol

V

Parameter

Differential Output Voltage

Magnitude Change

Offset Voltage

Magnitude Change

1.15

Test Conditions

Minimum

250

Typical

Maximum

450

1.45

Units

8SLVD1204 May 8, 2020

8SLVD1204 DATASHEET

AC Electrical Characteristics

Table 5. AC Electrical Characteristics,

= 2.5V ± 5%, T

= -40°C to 85°C

Symbol

REF

V/t

tsk(o)

tsk(i)

tsk(p)

tsk(pp)

Parameter

Input

Frequency

Input

Edge Rate

PCLK[0:1],

nPCLK[0:1]

PCLK[0:1],

nPCLK[0:1]

PCLK[0:1], nPCLK[0:1] to any Qx, nQx

for V

= 0.1V or 0.3V

1.5

120

210

300

REF

= 100MHz

230

REF

= 122.88MHz Square Wave, V

= 1V,

Integration Range: 1kHz – 40MHz

REF

= 122.88MHz Square Wave, V

= 1V,

Integration Range: 10kHz – 20MHz

REF

= 122.88MHz Square Wave, V

= 1V,

Integration Range: 12kHz – 20MHz

Buffer Additive Phase

Jitter, RMS; refer to

Additive Phase Jitter

Section

REF

= 156.25MHz Square Wave, V

= 1V,

Integration Range: 1kHz – 40MHz

REF

= 156.25MHz Square Wave, V

= 1V,

Integration Range: 10kHz – 20MHz

REF

= 156.25MHz Square Wave, V

= 1V,

Integration Range: 12kHz – 20MHz

REF

= 156.25MHz Square Wave, V

= 0.5V,

Integration Range: 1kHz – 40MHz

REF

= 156.25MHz Square Wave, V

= 0.5V,

Integration Range: 10kHz – 20MHz

REF

= 156.25MHz Square Wave, V

= 0.5V,

Integration Range: 12kHz – 20MHz

/ t

MUX

ISOLATION

Output Rise/ Fall Time

Mux Isolation; NOTE 5

20% to 80%

outputs loaded with 100

REF

= 100MHz

138

205

135

130

250

Test Conditions

Minimum

Typical

Maximum

Units

GHz

V/ns

Propagation Delay;

NOTE 1

Output Skew; NOTE 2, 3

Input Skew; NOTE 3

Pulse Skew

Part-to-Part Skew;

NOTE 3, 4

JIT

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device

is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal

equilibrium has been reached under these conditions.

NOTE 1: Measured from the differential input crosspoint to the differential output crosspoint.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoint.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and

with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoint.

NOTE 5: Qx, nQx outputs measured differentially. See

MUX Isolation diagram

in the

Parameter Measurement Information section.

8SLVD1204 May 8, 2020

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8SLVD1204NLGI/W Related Products

	8SLVD1204NLGI/W	8SLVD1204NLGI	8SLVD1204NLGI8
Description	Low Skew Clock Driver, 8SLVD Series, 8 True Output(s), 0 Inverted Output(s), CMOS	Low Skew Clock Driver, 8SLVD Series, 8 True Output(s), 0 Inverted Output(s), CMOS	Low Skew Clock Driver, 8SLVD Series, 8 True Output(s), 0 Inverted Output(s), CMOS
Is it Rohs certified?	conform to	conform to	conform to
Maker	Renesas Electronics Corporation	Renesas Electronics Corporation	Renesas Electronics Corporation
package instruction	HQCCN,	HQCCN,	HQCCN,
Reach Compliance Code	compli	compliant	compliant
Other features	SEATED HT CALCULATED	SEATED HT CALCULATED	SEATED HT CALCULATED
series	8SLVD	8SLVD	8SLVD
Input adjustment	DIFFERENTIAL MUX	DIFFERENTIAL MUX	DIFFERENTIAL MUX
JESD-30 code	S-XQCC-N16	S-XQCC-N16	S-XQCC-N16
JESD-609 code	e3	e3	e3
length	3 mm	3 mm	3 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER
Humidity sensitivity level	3	1	3
Number of functions	1	1	1
Number of terminals	16	16	16
Actual output times	8	8	8
Maximum operating temperature	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C
Package body material	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
encapsulated code	HQCCN	HQCCN	HQCCN
Package shape	SQUARE	SQUARE	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG	CHIP CARRIER, HEAT SINK/SLUG	CHIP CARRIER, HEAT SINK/SLUG
Peak Reflow Temperature (Celsius)	260	260	260
propagation delay (tpd)	0.3 ns	0.3 ns	0.3 ns
Same Edge Skew-Max（tskwd）	0.02 ns	0.02 ns	0.02 ns
Maximum seat height	1.05 mm	1.05 mm	1.05 mm
Maximum supply voltage (Vsup)	2.625 V	2.625 V	2.625 V
Minimum supply voltage (Vsup)	2.375 V	2.375 V	2.375 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Matte Tin (Sn)	Matte Tin (Sn) - annealed	Matte Tin (Sn)
Terminal form	NO LEAD	NO LEAD	NO LEAD
Terminal pitch	0.5 mm	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	3 mm	3 mm	3 mm

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