R5F52105BGFN datasheet, PDF - EEWORLD Datasheet

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R5F52105BGFN: DescriptionMICROCONTROLLER; CategoryThe embedded processor and controller Microcontrollers and processors; File Size6MB，223 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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R5F52105BGFN Overview

MICROCONTROLLER

R5F52105BGFN Parametric

Parameter Name	Attribute value
Maker	Renesas Electronics Corporation
Reach Compliance Code	compli
Has ADC	YES
Address bus width
bit size	32
CPU series	RX
maximum clock frequency	20 MHz
DMA channel	YES
External data bus width
JESD-30 code	S-PQFP-G80
length	12 mm
Number of I/O lines	64
Number of terminals	80
Maximum operating temperature	105 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP80,.55SQ,20
Package shape	SQUARE
Package form	FLATPACK
power supply	1.8/5 V
Certification status	Not Qualified
RAM (bytes)	20480
rom(word)	131072
ROM programmability	FLASH
speed	50 MHz
Maximum slew rate	55 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	2.7 V
Nominal supply voltage	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
width	12 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER

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Datasheet

RX210 Group

Renesas MCUs

R01DS0041EJ0150

Rev.1.50

Oct 18, 2013

50-MHz 32-bit RX MCUs, 78 DMIPS, up to 1-MB flash memory,

12-bit A/D, 10-bit D/A, ELC, MPC, RTC, up to 15 comms channels;

incorporating functions for IEC60730 compliance

Features

■

32-bit RX CPU core



Max. operating frequency: 50 MHz

Capable of 78 DMIPS in operation at 50 MHz

Accumulator handles 64-bit results (for a single instruction)

from 32- × 32-bit operations

Multiplication and division unit handles 32- × 32-bit

operations (multiplication instructions take one CPU clock

cycle)

Fast interrupt

CISC Harvard architecture with 5-stage pipeline

Variable-length instructions, ultra-compact code

On-chip debugging circuit

Operation from a single 1.62-V to 5.5-V supply

1.62-V operation available (at up to 20 MHz)

Deep software standby mode with RTC remaining usable

Four low power consumption modes

50-MHz operation, 20-ns read cycle

No wait states for reading at full CPU speed

64-K to 1-Mbyte capacities

User code programmable via the SCI

Programmable at 1.62 V

For instructions and operands

8 Kbytes

(Number of times of reprogramming: 100,000)

Erasing and programming impose no load on the CPU.

12-K to 96-Kbyte size capacities

DMAC: Incorporates four channels

DTC: Four transfer modes

Module operation can be initiated by event signals without

going through interrupts.

Modules can operate while the CPU is sleeping.

Nine types of reset, including the power-on reset (POR)

Low voltage detection (LVD) with voltage settings

Frequency of external clock: Up to 20 MHz

Frequency of the oscillator for sub-clock generation: 32.768

kHz

PLL circuit input: 4 MHz to 12.5 MHz

On-chip low- and high-speed oscillators, dedicated on-chip

low-speed oscillator for the IWDT

Generation of a dedicated 32.768-kHz clock for the RTC

Clock frequency accuracy measurement circuit (CAC)

Adjustment functions (30 seconds, leap year, and error)

Year and month display or 32-bit second display (binary

counter) is selectable

Time capture function

Time capture on event-signal input through external pins

RTC capable of initiating return from deep software standby

mode

125-kHz on-chip oscillator produces a dedicated clock signal

to drive IWDT operation.

PLQP0144KA-A 20 × 20 mm, 0.5-mm pitch

PLQP0100KB-A 14 × 14 mm, 0.5-mm pitch

PLQP0080KB-A 12 × 12 mm, 0.5-mm pitch

PLQP0064KB-A 10 × 10 mm, 0.5-mm pitch

PLQP0048KB-A 7 × 7 mm, 0.5-mm pitch

PLQP0080JA-A 14 × 14 mm, 0.65-mm pitch

PLQP0064GA-A 14 × 14 mm, 0.8-mm pitch

PTLG0145KA-A

PTLG0100JA-A

PTLG0100KA-A

PTLG0064JA-A

SWBG0069LA-A

7 × 7 mm, 0.5-mm pitch

7 × 7 mm, 0.65-mm pitch

5.5 × 5.5 mm, 0.5-mm pitch

6 × 6 mm, 0.65-mm pitch

3.91 × 4.26mm,

0.40-mm pitch

■

Low power design and architecture

■

Useful functions for IEC60730 compliance



Self-diagnostic and disconnection-detection assistance

functions for the A/D converter, clock frequency accuracy

measurement circuit, independent watchdog timer, functions

to assist in RAM testing, etc.

SCI with many useful functions (up to 13 channels)

Asynchronous mode, clock synchronous mode, smart card

interface

C bus interface: Transfer at up to 400 kbps, capable of

SMBus operation (one channel)

RSPI (one channel): Transfer at up to 16 Mbps (768-Kbyte/

1-Mbyte flash memory or 144/145-pin products)

Four CS areas (4 × 16 Mbytes)

8- or 16-bit bus space is selectable per area

16-bit MTU: input capture, output compare, complementary

PWM output, phase counting mode

(six channels)

16-bit TPU: input capture, output capture, phase counting

mode (six channels)

8-bit TMR (four channels)

16-bit compare-match timers (four channels)

Capable of conversion within 1

μs

Sample-and-hold circuits (for three channels)

Three-channel synchronized sampling available

Self-diagnostic function and analog input disconnection

detection assistance function

■

On-chip flash memory for code, no wait states

■

Up to 15 communications channels



■

On-chip data flash memory

■

External address space



■

On-chip SRAM, no wait states

■

DMA

■

Up to 20 extended-function timers

■

ELC

■

12-bit A/D converter

■

Reset and supply management

■

Clock functions

■

10-bit D/A converter

■

Analog comparator

■

General I/O ports



5-V tolerant, open drain, input pull-up, switching of driving

ability

Multiple locations are selectable for I/O pins of peripheral

functions

■

MPC



■

Realtime clock

■

Temperature sensor

■

Operating temp. range



40C

to +85C

40C

to +105C



■

Applications

69WLBGA (SWBG0069LA-A): General consumer

equipment

Other than above package: General industrial and consumer

equipment

■

Independent watchdog timer



R01DS0041EJ0150 Rev.1.50

Oct 18, 2013

Page 1 of 221

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