Features
Preliminary
Datasheet
Specifications in this document are tentative and subject to change.
RX64M Group
Renesas MCUs
120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 4-MB flash memory,
512-KB SRAM, various communications interfaces including IEEE 1588-compliant Ethernet MAC,
full-speed USB 2.0 with battery charging, SD host interface (optional), quad SPI, and CAN, 12-bit A/D
converter, RTC, encryption (optional), serial interface for audio, CMOS camera interface
R01DS0173EJ0090
Rev.0.90
Feb 28, 2014
Features
■
32-bit RXv2 CPU core
Max. operating frequency: 120 MHz
Capable of 240 DMIPS in operation at 120 MHz
Single precision 32-bit IEEE-754 floating point
Two types of multiply-and-accumulation unit (between memories
and between registers)
32-bit multiplier (fastest instruction execution takes one CPU clock
cycle)
Divider (fastest instruction execution takes two CPU clock cycles)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Variable-length instructions: Ultra-compact code
Supports the memory protection unit (MPU)
JTAG and FINE (two-line) debugging interfaces
Operation from a single 2.7- to 3.6-V supply
Low power consumption: A product that supports all peripheral
functions draws only 0.3mA/MHz (Typ.).
RTC is capable of operation from a dedicated power supply.
Four low-power modes
Supports versions with up to 4 Mbytes of ROM
120-MHz operation, 8.3-ns read cycle (no wait states)
User code is programmable by on-board or off-board programming.
Programming/erasing as background operations (BGOs)
PLQP0176KB-A 24 × 24 mm, 0.5-mm pitch
PLQP0144KA-A 20 × 20 mm, 0.5-mm pitch
PLQP0100KB-A 14 × 14 mm, 0.5-mm pitch
PTLG0177KA-A 8 × 8 mm, 0.5-mm pitch
PTLG0145KA-A 7 × 7 mm, 0.5-mm pitch
PTLG0100JA-A 7 × 7 mm, 0.65-mm pitch
PLBG0176GA-A 13 × 13mm, 0.8-mm pitch
■
Various communications interfaces
■
Low-power design and architecture
■
On-chip code flash memory, no wait states
■
On-chip data flash memory
Max. 64 Kbytes, reprogrammable up to 100,000 times
Programming/erasing as background operations (BGOs)
512 Kbytes of SRAM (no wait states)
32 Kbytes of RAM with ECC (one wait state, single-error correction
and double error detection)
8 Kbytes of standby RAM (backup on deep software standby)
DMAC: 8 channels
DTC
EXDMAC: 2 channels
DMAC for the Ethernet controller: 2 channels for 176- and 177-pin
products; 1 channel for 100-, 144-, and 145-pin products
■
On-chip SRAM
Ethernet MAC (for 176- and 177-pin products: 2 modules)
PHY layer for host/function or OTG controller (1) with full-speed
USB 2.0 with battery charging transfer (only for 176- and 177-pin
products)
PHY layer (1) for host/function or OTG controller (1) with full-
speed USB 2.0 transfer
CAN (compliant with ISO11898-1), incorporating 32 mailboxes (up
to 3 modules)
SCIg and SCIh with multiple functionalities (up to 9)
Choose from among asynchronous mode, clock-synchronous mode,
smart-card interface mode, simplified SPI, simplified I
2
C, and
extended serial mode.
SCIFA with 16-byte transmission and reception FIFOs (up to 4
interfaces)
I
2
C bus interface for transfer at at up to 1 Mbps (up to 2 interfaces)
Four-wire QSPI (1 interface) in addition to RSPIa (1 interface)
Parallel data capture unit (PDC) for the CMOS camera interface (not
in 100-pin products)
SD host interface (optional: 1 interface) with a 1- or 4-bit SD bus for
use with SD memory or SDIO
Buses for full-speed data transfer (max. operating frequency of 60
MHz)
8 CS areas
8-, 16-, or 32-bit bus space is selectable per area
Independent SDRAM area (128 Mbytes)
16-bit TPUa, MTU3a, and GPTA: input capture, output compare,
PWM waveform output
8-bit TMRa (4 channels), 16-bit CMT (4 channels), 32-bit CMTW (2
channels)
Two 12-bit units (8 channels for unit 0; 21 channels for unit 1)
Self diagnosis
Detection of analog input disconnection
On-chip operational amplifier output or direct input selectable
■
External address space
■
Data transfer
■
Up to 29 extended-function timers
■
Reset and supply management
Power-on reset (POR)
Low voltage detection (LVD) with voltage settings
External crystal oscillator or internal PLL for operation at 8 to 24
MHz
Internal 240-kHz LOCO and HOCO selectable from 16, 18, and 20
MHz
120-kHz clock for the IWDTa
Adjustment functions (30 seconds, leap year, and error)
Real-time clock counting and binary counting modes are selectable
Time capture function
(for capturing times in response to event-signal input)
120-kHz (1/2 LOCO frequency) clock operation
■
Clock functions
■
12-bit A/D converter
■
12-bit D/A converter: 2 channels
■
Real-time clock
■
Temperature sensor for measuring temperature
within the chip
■
Encryption (optional)
■
Independent watchdog timer
AES (key lengths: 128, 196, and 256 bits)
DES (key lengths: 56 bits (DES); 3 × 56 bits (T-DES))
SHA (SHA-1 (128), SHA-2 (224 or 256), HMAC (160, 224, or 256))
5-V tolerance, open drain, input pull-up, switchable driving ability
–40C to +85C
■
Useful functions for IEC60730 compliance
Oscillation-stoppage detection, frequency measurement, CRC,
IWDTa, self-diagnostic function for the A/D converter, etc.
Register write protection function can protect values in important
registers against overwriting.
■
Up to 127 pins for general I/O ports
■
Operating temp. range
R01DS0173EJ0090 Rev.0.90
Feb 28, 2014
Page 1 of 67
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RX64M Group
1. Overview
1.
1.1
Overview
Outline of Specifications
Table 1.1
lists the specifications in outline, and
Table 1.2
gives a comparison of the functions of products in different
packages.
Table 1.1
shows the outline of maximum specifications, and the number of peripheral module channels differs
depending on the pin number on the package and the code flash memory capacity. For details, see
Table 1.2,
Comparison of Functions for Different Packages.
Table 1.1
Classification
CPU
Outline of Specifications (1/9)
Module/Function
CPU
Description
Maximum operating frequency: 120 MHz
32-bit RX CPU (RX v2)
Minimum instruction execution time: One instruction per state (cycle of the system
clock)
Address space: 4-Gbyte linear
Register set of the CPU
General purpose: Sixteen 32-bit registers
Control: Ten 32-bit registers
Accumulator: Two 72-bit registers
Basic instructions: 75
Floating-point instructions: 11
DSP instructions: 23
Addressing modes: 10
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
On-chip 32-bit multiplier: 32 × 32
→
64 bits
On-chip divider: 32 / 32
→
32 bits
Barrel shifter: 32 bits
Single precision (32-bit) floating point
Data types and floating-point exceptions in conformance with the IEEE754 standard
Capacity: 2 Mbytes, 2.5 Mbytes, 3 Mbytes, 4 Mbytes
120 MHz, no-wait access
On-board programming: Four types
Off-board programming (parallel programmer mode)
FPU
Memory
Flash memory
(code flash)
E2 data flash
RAM
RAM with ECC
Capacity: 64 Kbytes
Programming/erasing: 100,000 times
Capacity: 512 Kbytes
120 MHz, no-wait access
Capacity: 32 Kbytes
120 MHz, single wait access
SEC-DED (single error correction/double error detection)
Capacity: 8 Kbytes
Operation synchronized with PCLKB: Up to 60 MHz, two-cycle access
Operating modes by the mode-setting pins
Single-chip mode
Boot mode (for the SCI interface)
Boot mode (for the USB interface)
User boot mode
Operating modes by register setting
Single-chip mode, user boot mode
On-chip ROM disabled extended mode
On-chip ROM enabled extended mode
Endian selectable
Standby RAM
Operating modes
R01DS0173EJ0090 Rev.0.90
Feb 28, 2014
Page 2 of 67
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RX64M Group
Table 1.1
Classification
Clock
1. Overview
Outline of Specifications (2/9)
Module/Function
Clock generation circuit
Description
Main clock oscillator, sub clock oscillator, low-speed/high-speed on-chip oscillator, PLL
frequency synthesizer, and IWDT-dedicated on-chip oscillator
Main-clock oscillation stoppage detection
Separate frequency-division and multiplication settings for the system clock (ICLK),
peripheral module clock (PCLKA, PCLKB, PCLKC, PCLKD), flash-IF clock (FCLK) and
external bus clock (BCLK)
The CPU and other bus masters run in synchronization with the system clock (ICLK):
Up to 120 MHz
Peripheral modules of MTU3, GPT, RSPI, SCIFA, USBA, ETHERC, EPTPC, EDMAC,
and AES run in synchronization with PCLKA, which operates at up to 120 MHz.
Other peripheral modules run in synchronization with PCLKB: Up to 60 MHz
ADCLK in the SD12AD (unit 0) runs in synchronization with PCLKC: Up to 60 MHz
ADCLK in the SD12AD (unit 1) runs in synchronization with PCLKD: Up to 60 MHz
Flash IF run in synchronization with the flash-IF clock (FCLK): Up to 60 MHz
Devices connected to the external bus run in synchronization with the external bus
clock (BCLK): Up to 60 MHz
Multiplication is possible with using the high-speed on-chip oscillator (HOCO) as a
reference clock of the PLL circuit
Nine types of reset
RES# pin reset: Generated when the RES# pin is driven low.
Power-on reset: Generated when the RES# pin is driven high and VCC = AVCC0 =
AVCC1 rises.
Voltage-monitoring 0 reset: Generated when VCC = AVCC0 = AVCC1 falls.
Voltage-monitoring 1 reset: Generated when VCC = AVCC0 = AVCC1 falls.
Voltage-monitoring 2 reset: Generated when VCC = AVCC0 = AVCC1 falls.
Deep software standby reset: Cancels deep software standby mode by an interrupt.
Independent watchdog timer reset: Generated when the independent watchdog timer
underflows, or a refresh error occurs.
Watchdog timer reset: Generated when the watchdog timer underflows, or a refresh
error occurs.
Software reset: Generated by register setting.
If the RES# pin is at the high level when power is supplied, an internal reset is generated.
After VCC = AVCC0 = AVCC1 has exceeded the voltage detection level and the specified
period has elapsed, the reset is cancelled.
Monitors the voltage being input to the VCC = AVCC0 = AVCC1 pins and generates an
internal reset or internal interrupt.
Voltage detection circuit 0
Capable of generating an internal reset
The option-setting memory can be used to select enabling or disabling of the reset.
Voltage detection level: Selectable from three different levels (2.94 V, 2.87 V, and 2.80
V)
Voltage detection circuits 1 and 2
Voltage detection level: Selectable from three different levels (2.99 V, 2.92 V, and 2.85
V)
Digital filtering (1/2, 1/4, 1/8, and 1/16 LOCO frequency)
Capable of generating an internal reset
Two types of timing are selectable for release from reset
An internal interrupt can be requested.
Detection of voltage rising above and falling below thresholds is selectable.
Maskable or non-maskable interrupt is selectable
Voltage detection monitoring
Event linking
Module stop function
Four low power consumption modes
Sleep mode, all-module clock stop mode, software standby mode, and deep software
standby mode
When the voltage on the VCC pin drops, battery power from the VBATT pin is supplied
to keep the real-time clock operating.
Reset
Power-on reset
Voltage detection circuit (LVDA)
Low power
consumption
Low power
consumption facilities
Battery backup function
R01DS0173EJ0090 Rev.0.90
Feb 28, 2014
Page 3 of 67
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RX64M Group
Table 1.1
Classification
Interrupt
1. Overview
Outline of Specifications (3/9)
Module/Function
Interrupt controller
(ICUA)
Description
Peripheral function interrupts: 293 sources
External interrupts: 16 (pins IRQ0 to IRQ15)
Software interrupts: 2 sources
Non-maskable interrupts: 7 sources
Sixteen levels specifiable for the order of priority
Method of interrupt source selection:
The interrupt vectors consist of 256 vectors (128 sources are fixed. The remaining 128
vectors are selected from among the other 156 sources.)
External bus extension
The external address space can be divided into eight areas (CS0 to CS7), each with
independent control of access settings.
Capacity of each area: 16 Mbytes (CS0 to CS7)
A chip-select signal (CS0# to CS7#) can be output for each area.
Each area is specifiable as an 8-, 16-, or 32-bit bus space.
The data arrangement in each area is selectable as little or big endian (only for data).
SDRAM interface connectable
Bus format: Separate bus, multiplex bus
Wait control
Write buffer facility
8 channels
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Software trigger, external interrupts, and interrupt requests from
peripheral functions
2 channels
Four transfer modes: Normal transfer, repeat transfer, block transfer, and cluster
transfer
Single-address transfer enabled with the EDACKn signal
Activation sources: Software trigger, external DMA requests (EDREQn), and interrupt
requests from peripheral functions
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: External interrupts and interrupt requests from peripheral functions
I/O ports for the 177-pin TFLGA (in planning), 176-pin LFBGA (in planning), and 176-pin
LQFP
I/O pins: 127
Input pin: 1
Pull-up resistors: 127
Open-drain outputs: 127
5-V tolerance: 19
I/O ports for the 145-pin TFLGA (in planning) and 144-pin LQFP
I/O pins: 111
Input pin: 1
Pull-up resistors: 111
Open-drain outputs: 111
5-V tolerance: 18
I/O ports for the 100-pin TFLGA (in planning) and 100-pin LQFP
I/O pins: 78
Input pin: 1
Pull-up resistors: 78
Open-drain outputs: 78
5-V tolerance: 17
Event signals such as interrupt request signals can be interlinked with the operation of
functions such as timer counting, eliminating the need for intervention by the CPU to
control the functions.
119 internal event signals can be freely combined for interlinked operation with
connected functions.
Event signals from peripheral modules can be used to change the states of output pins
(of ports B and E).
Changes in the states of pins (of ports B and E) being used as inputs can be interlinked
with the operation of peripheral modules.
DMA
DMA controller
(DMACAa)
EXDMA controller
(EXDMACa)
Data transfer controller
(DTCa)
I/O ports
Programmable I/O ports
Event link controller (ELC)
R01DS0173EJ0090 Rev.0.90
Feb 28, 2014
Page 4 of 67
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RX64M Group
Table 1.1
Classification
Timers
1. Overview
Outline of Specifications (4/9)
Module/Function
16-bit timer pulse unit
(TPUa)
Description
(16 bits × 6 channels) × 1 unit
Maximum of 16 pulse-input/output possible
Select from among seven or eight counter-input clock signals for each channel
Input capture/output compare function
Output of PWM waveforms in up to 15 phases in PWM mode
Support for buffered operation, phase-counting mode (two phase encoder input) and
cascade-connected operation (32 bits × 2 channels) depending on the channel.
PPG output trigger can be generated
Capable of generating conversion start triggers for the A/D converters
Digital filtering of signals from the input capture pins
Event linking by the ELC
Timers
Multifunction timer
pulse unit (MTU3a)
9 channels (16 bits × 8 channels, 32 bits × 1 channel)
Maximum of 16 pulse-input/output and 3 pulse-input possible
Select from among 13 counter-input clock signals for each channel (PCLKA/1, PCLKA/
2, PCLKA/4, PCLKA/8, PCLKA/16, PCLK/A32, PCLKA/64, PCLKA/256, PCLKA/1024,
MTCLKA, MTCLKB, MTCLKC, MTCLKD)
11 of the signals are available for channels 1, 3 and 4, 12 are available for channel 2,
and 9 are available for channels 5 to 8.
Input capture function
39 output compare/input capture registers
Counter clear operation (synchronous clearing by compare match/input capture)
Simultaneous writing to multiple timer counters (TCNT)
Simultaneous register input/output by synchronous counter operation
Buffered operation
Support for cascade-connected operation
43 interrupt sources
Automatic transfer of register data
Pulse output mode
Toggle/PWM/complementary PWM/reset-synchronized PWM
Complementary PWM output mode
Outputs non-overlapping waveforms for controlling 3-phase inverters
Automatic specification of dead times
PWM duty cycle: Selectable as any value from 0% to 100%
Delay can be applied to requests for A/D conversion.
Non-generation of interrupt requests at peak or trough values of counters can be
selected.
Double buffer configuration
Reset synchronous PWM mode
Three phases of positive and negative PWM waveforms can be output with desired duty
cycles.
Phase-counting mode: 16-bit mode (channels 1 and 2); 32-bit mode (channels 1 and 2)
Counter functionality for dead-time compensation
Generation of triggers for A/D converter conversion
A/D converter start triggers can be skipped
Digital filter function for signals on the input capture and external counter clock pins
PPG output trigger can be generated
Event linking by the ELC
Control of the high-impedance state of the MTU3/GPT's waveform output pins
5 pins for input from signal sources: POE0, POE4, POE8, POE10, POE11
Initiation on detection of short-circuited outputs (detection of simultaneous PWM output
to the active level)
Initiation by oscillation-stoppage detection or software
Additional programming of output control target pins is enabled
Port output enable 3
(POE3a)
R01DS0173EJ0090 Rev.0.90
Feb 28, 2014
Page 5 of 67
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