DATASHEET
X9401
Low Noise/Low Power/SPI Bus Quad, 64 Tap, Digitally Controlled Potentiometer
(XDCP™)
FN8190
Rev 5.00
September 14, 2015
Description
The X9401 integrates 4 digitally controlled potentiometers
(XDCP) on a monolithic CMOS integrated microcircuit.
The digitally controlled potentiometer is implemented using
64 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the SPI bus interface. Each
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and 4 nonvolatile Data Registers
(DR0:DR3) that can be directly written to and read by the
user. The contents of the WCR controls the position of the
wiper on the resistor array through the switches. Power-up
recalls the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Features
• Quad - 4 Separate Pots, 64 Taps/Pot
• Nonvolatile Storage of Wiper Position
• Four Nonvolatile Data Registers for Each Pot
• 16-bytes of EEPROM Memory
• SPI Serial Interface
• R
TOTAL
= 10k
• Wiper Resistance = 150 Typical
• Standby Current < 3µA (Total Package)
• Operating Current < 700µA max.
• V
CC
= 2.7V to 5V
• 24 Ld SOIC and 24 Ld TSSOP Package
• 100 year Data Retention
• Pb-Free Available (RoHS Compliant)
Block Diagram
V
CC
V
SS
R0
R1
POT 0
WIPER
COUNTER
REGISTER
(WCR)
V
H0
/R
H0
R0
R1
WIPER
COUNTER
REGISTER
(WCR)
V
H2
/R
H2
HOLD
CS
SCK
SO
SI
A0
A1
WP
INTERFACE
AND
CONTROL
CIRCUITRY
DATA
R2
R3
V
L0
/R
L0
V
W0
/R
W0
R2
R3
RESISTOR
ARRAY
POT 2
V
L2
/R
L2
V
W2
/R
W2
8
V
W1
/R
W1
R0
R1
WIPER
COUNTER
REGISTER
(WCR)
V
H1
/R
H1
R0
R1
V
W3
/R
W3
WIPER
COUNTER
REGISTER
(WCR)
V
H3
/R
H3
RESISTOR
ARRAY
POT 1
R2
R3
V
L1
/R
L1
R2
R3
RESISTOR
ARRAY
POT 3
V
L3
/R
L3
FN8190 Rev 5.00
September 14, 2015
Page 1 of 20
X9401
Ordering Information
PART
NUMBER
X9401WS24IZ* (Note 1)
(No longer available,
recommended
replacement:
X9401WS24IZ-2.7T1)
PART
MARKING
X9401WS ZI
V
CC
LIMITS
(V)
5 ±10%
POTENTIOMETER
ORGANIZATION
(k)
10
TEMP
RANGE
(°C)
-40 to +85
PACKAGE
24 Ld SOIC (300 mil) (Pb-free)
PKG.
DWG. #
M24.3
X9401WS24Z* (Note 1)
(No
X9401WS Z
longer available,
recommended
replacement:
X9401WS24IZ-2.7T1)
X9401WV24IZ* (Note 1)
(No longer available,
recommended
replacement:
X9401WV24IZ-2.7T1)
X9401WV ZI
-40 to +85
24 Ld SOIC (300 mil)
M24.3
-40 to +85
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9401WV24Z* (Note 1)
(No
X9401WV Z
longer available,
recommended
replacement:
X9401WV24IZ-2.7T1)
X9401WS24IZ-2.7* (Note)
X9401WS ZG
2.7 to 5.5
-40 to +85
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
-40 to +85
-40 to +85
24 Ld SOIC (300 mil) (Pb-free)
24 Ld SOIC (300 mil) (Pb-free)
M24.3
M24.3
X9401WS24Z-2.7* (Note 1) X9401WS ZF
(No longer available,
recommended
replacement:
X9401WS24IZ-2.7T1)
X9401WV24IZ-2.7* (Note 1) X9401WV ZG
X9401WV24Z-2.7* (Note 1) X9401WV ZF
(No longer available,
recommended
replacement:
X9401WV24IZ-2.7T1)
NOTES:
-40 to +85
-40 to +85
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
*Add “T1” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J STD-020.
2. Not recommended for new designs.
Pin Descriptions
Host Interface Pins
SERIAL OUTPUT (SO)
SO is a push/pull serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by the falling
edge of the serial clock.
SERIAL INPUT
SI is the serial data input pin. All opcodes, byte addresses and
data to be written to the pots and pot registers are input on this
pin. Data is latched by the rising edge of the serial clock.
SERIAL CLOCK (SCK)
The SCK input is used to clock data into and out of the X9401.
CHIP SELECT (CS)
When CS is HIGH, the X9401 is deselected and the SO pin is
at high impedance, and (unless an internal write cycle is
underway) the device will be in the standby state. CS LOW
enables the X9401, placing it in the active power mode. It
should be noted that after a power-up, a HIGH to LOW
transition on CS is required prior to the start of any operation.
FN8190 Rev 5.00
September 14, 2015
Page 2 of 20
X9401
HOLD (HOLD)
HOLD is used in conjunction with the CS pin to select the
device. Once the part is selected and a serial sequence is
underway, HOLD may be used to pause the serial
communication with the controller without resetting the serial
sequence. To pause, HOLD must be brought LOW while SCK
is LOW. To resume communication, HOLD is brought HIGH,
again while SCK is LOW. If the pause feature is not used,
HOLD should be held HIGH at all times.
DEVICE ADDRESS (A
0
-
A
1
)
The address inputs are used to set the least significant 2 bits of the 8-
bit slave address. A match in the slave address serial data stream
must be made with the address input in order to initiate
communication with the X9401. A maximum of 4 devices may
occupy the SPI serial bus.
SI 1
A
1
2
V
L1
/R
L1
3
V
H1
/R
H1
4
V
W1
/R
W1
5
V
SS
6
NC 7
V
W2
/R
W2
8
V
H2
/R
H2
9
V
L2
/R
L2
10
SCK 11
HOLD 12
(24 LD TSSOP)
TOP VIEW
24 WP
23 CS
22 V
W0
/R
W0
21 V
H0
/R
H0
20 V
L0
/R
L0
19 V
CC
18 NC
17 V
L3
/R
L3
16 V
H3
/R
H3
15 V
W3
/R
W3
14 A
0
13 S0
Potentiometer Pins
V
H
(V
H0
- V
H3
)/ R
H
(R
H0
- R
H3
),
V
L
(V
L0
- V
L3
)/R
L
(R
L0
- R
L3
)
The V
H
/R
H
and V
L
/R
L
inputs are equivalent to the terminal
connections on either end of a mechanical potentiometer.
VW (VW0 - VW3)/ RW (RW0 - RW3)
The wiper outputs are equivalent to the wiper output of a
mechanical potentiometer.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when LOW prevents nonvolatile writes to the
Wiper Counter Registers.
Pin Descriptions
SOIC TSSOP
PIN # PIN #
5
17
7, 19
20, 8
23
11
1, 13
14, 2
SYMBOL
CS
SCK
SI, S0
A
0
- A
1
DESCRIPTION
Chip select
Serial Clock
Serial Data
Device Address
3, 10, 21, 4,
15, 22, 9, 16,
20, 3,
2, 9,
16, 23 10, 17
4, 11,
14, 21
6
18
1
12
22, 5,
8, 15
24
12
19
6
7, 18
V
H0
/R
H0,
V
H1
/R
H1,
Potentiometer end
V
H2
/R
H2
, V
H3
/R
H3
, terminals
V
L0
/R
L0,
V
L1
/R
L1
,
V
L2
/R
L2,
V
L3
/R
L3
V
W0
/R
W0,
V
W1
/R
W1,
Wipers
V
W2
/R
W2,
V
W3
/R
W3
WP
HOLD
V
CC
V
SS
NC
Hardware Write Protection
Hardware Hold
System Supply Voltage
System Ground
No Connection
Pinouts
X9401
(24 LD SOIC)
TOP VIEW
V
CC
1
V
L0
/R
L0
2
V
H0
/R
H0
3
V
W0
/R
W0
4
CS 5
WP 6
SI 7
A
1
8
V
L1
/R
L1
9
V
H1
/R
H1
10
V
W1
/R
W1
11
V
SS
12
24 NC
23 V
L3
/R
L3
22 V
H3
/R
H3
21 V
W3
/R
W3
20 A
0
19 S0
18 HOLD
17 SCK
16 V
L2
/R
L2
15 V
H2
/R
H2
14 V
W2
/R
W2
13 NC
13, 24
Device Description
The X9401 is a highly integrated microcircuit incorporating four
resistor arrays and their associated registers and counters and
the serial interface logic providing direct communication
between the host and the XDCP potentiometers.
Serial Interface
The X9401 supports the SPI interface hardware conventions.
The device is accessed via the SI input with data clocked in on
the rising SCK. CS must be LOW and the HOLD and WP pins
must be HIGH during the entire operation.
The SO and SI pins can be connected together, since they
have three state outputs. This can help to reduce system pin
count.
X9401
Array Description
The X9401 is comprised of four resistor arrays. Each array
contains 63 discrete resistive segments that are connected in
FN8190 Rev 5.00
September 14, 2015
Page 3 of 20
X9401
series. The physical ends of each array are equivalent to the
fixed terminals of a mechanical potentiometer (V
H
/R
H
and
V
L
/R
L
inputs).
At both ends of each array and between each resistor segment
is a CMOS switch connected to the wiper (V
W
/R
W
) output.
Within each individual array only one switch may be turned on
at a time.
These switches are controlled by a Wiper Counter Register
(WCR). The six bits of the WCR are decoded to select, and
enable, one of sixty-four switches.
progress of this internal write operation can be monitored by a
Write In Process bit (WIP). The WIP bit is read with a Read
Status command.
Instructions
Identification (ID) Byte
The first byte sent to the X9401 from the host, following a CS
going HIGH to LOW, is called the Identification byte. The most
significant four bits of the slave address are a device type
identifier. For the X9401 this is fixed as 0101[B] (refer to Figure
1).
The two least significant bits in the ID byte select one of four
devices on the bus. The physical device address is defined by
the state of the A
0
- A
1
input pins. The X9401 compares the
serial data stream with the address input state; a successful
compare of both address bits is required for the X9401 to
successfully continue the command sequence. The A
0
- A
1
inputs can be actively driven by CMOS input signals or tied to
V
CC
or V
SS
. The remaining two bits in the slave byte must be
set to 0.
DEVICE TYPE
IDENTIFIER
Wiper Counter Register (WCR)
The X9401 contains four Wiper Counter Registers, one for
each XDCP potentiometer. The WCR is equivalent to a serial-
in, parallel-out register/counter with its outputs decoded to
select one of sixty-four switches along its resistor array. The
contents of the WCR can be altered in four ways: it may be
written directly by the host via the Write Wiper Counter
Register instruction (serial load); it may be written indirectly by
transferring the contents of one of four associated data
registers via the XFR Data Register or Global XFR Data
Register instructions (parallel load); it can be modified one step
at a time by the Increment/Decrement instruction. Finally, it is
loaded with the contents of its data register zero (R0) upon
power-up.
The Wiper Counter Register is a volatile register; that is, its
contents are lost when the X9401 is powered-down. Although
the register is automatically loaded with the value in R
0
upon
power-up, this may be different from the value present at
power-down. The wiper position must be stored in R
0
to insure
restoring the wiper position after power-up.
0
1
0
1
0
0
A1
A0
DEVICE ADDRESS
FIGURE 1. IDENTIFICATION BYTE FORMAT
Instruction Byte
The next byte sent to the X9401 contains the instruction and
register pointer information. The four most significant bits are
the instruction. The next four bits point to one of the four pots
and, when applicable, they point to one of four associated
registers. The format is shown below in Figure 2.
I
Data Registers
Each potentiometer has four 6-bit nonvolatile data registers.
These can be read or written directly by the host. Data can also
be transferred between any of the four data registers and the
associated Wiper Counter Register. All operations changing
data in one of the data registers is a nonvolatile operation and
will take a maximum of 10ms.
If the application does not require storage of multiple settings
for the potentiometer, the data registers can be used as
memory locations for system parameters or user preference
data.
DATA REGISTER DETAIL
(MSB)
D5
NV
D4
NV
D3
NV
D2
NV
D1
NV
(LSB)
D0
NV
I3
I2
I1
I0
R1
R0
P1
P0
INSTRUCTIONS
POT SELECT
FIGURE 2. IDENTIFICATION BYTE FORMAT
Write in Process
The contents of the Data Registers are saved to nonvolatile
memory when the CS pin goes from LOW to HIGH after a
complete write sequence is received by the device. The
The four high order bits of the instruction byte specify the
operation. The next two bits (R
1
and R
0
) select one of the four
registers that is to be acted upon when a register oriented
instruction is issued. The last two bits (P1 and P
0
) selects
which one of the four potentiometers is to be affected by the
instruction.
FN8190 Rev 5.00
September 14, 2015
Page 4 of 20
X9401
Four of the ten instructions are two bytes in length and end
with the transmission of the instruction byte. These instructions
are:
• XFR Data Register to Wiper Counter Register: This transfers
the contents of one specified Data Register to the associated
Wiper Counter Register.
• XFR Wiper Counter Register to Data Register: This transfers
the contents of the specified Wiper Counter Register to the
specified associated Data Register.
• Global XFR Data Register to Wiper Counter Register: This
transfers the contents of all specified Data Registers to the
associated Wiper Counter Registers.
• Global XFR Wiper Counter Register to Data
Register: This transfers the contents of all Wiper Counter
Registers to the specified associated Data Registers.
The basic sequence of the two byte instructions is illustrated in
Figure 3. These two-byte instructions exchange data between
the WCR and one of the data registers. A transfer from a data
register to a WCR is essentially a write to a static RAM, with
the static RAM controlling the wiper position. The response of
the wiper to this action will be delayed by t
WRL
. A transfer from
the WCR (current wiper position), to a data register is a write to
nonvolatile memory and takes a minimum of t
WR
to complete.
The transfer can occur between one of the four potentiometers
and one of its associated registers; or it may occur globally,
where the transfer occurs between all potentiometers and one
associated register.
Five instructions require a three-byte sequence to complete.
These instructions transfer data between the host and the
X9401; either between the host and one of the data registers or
directly between the host and the Wiper Counter Register.
These instructions are:
• Read Wiper Counter Register: read the current wiper
position of the selected pot,
• Write Wiper Counter Register: change current wiper position
of the selected pot,
• Read Data Register: read the contents of the selected data
register;
• Write Data Register: write a new value to the selected data
register.
• Read Status: This command returns the contents of the WIP
bit which indicates if the internal write cycle is in progress.
The sequence of these operations is shown in Figure 4 and
Figure 5.
The final command is Increment/Decrement. It is different from
the other commands, because it’s length is indeterminate.
Once the command is issued, the master can clock the
selected wiper up and/or down in one resistor segment steps;
thereby, providing a fine tuning capability to the host. For each
SCK clock pulse (t
HIGH
) while SI is HIGH, the selected wiper
will move one resistor segment towards the V
H
/R
H
terminal.
Similarly, for each SCK clock pulse while SI is LOW, the
selected wiper will move one resistor segment towards the
V
L
/R
L
terminal. A detailed illustration of the sequence and
timing for this operation are shown in Figure 6 and Figure 7.
FN8190 Rev 5.00
September 14, 2015
Page 5 of 20
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