High Reliability Series Serial EEPROM Series
I C BUS
Serial EEPROMs
BR24G□□
□
-3A Series
□□□
□□
☆
BR24G01-3A,
☆
BR24G02-3A,
☆
BR24G04-3A,
☆
BR24G08-3A,
☆
BR24G16-3A,
☆
BR24G32-3A,
☆
BR24G64-3A,
☆
BR24G1M-3A
☆
:BR24G01/02/04/08/16/32/64/512/1M-3A
are model, the description matters are target all specifications because of the
model under development.
2
BR24G128-3A, BR24G256-3A,
☆
BR24G512-3A,
ROHM's series of serial EEPROMs represent the highest level of reliability on the market. A double cell structure provides a
failsafe method of data reliability, while a double reset function prevents data miswriting, pushing the boundaries of reliability
to the limit.
Contents
BR24G□□
□
-3A Series
□□□
□□
BR24G01-3A, BR24G02-3A, BR24G04-3A, BR24G08-3A,
BR24G16-3A, BR24G32-3A, BR24G64-3A, BR24G128-3A,
BR24G256-3A, BR24G512-3A, BR24G1M-3A
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© 2012 ROHM Co., Ltd. All rights reserved.
1/20
2012.2 - Rev.C
BR24G□□□
□□□-3A
Series
□□□
Technical Note
I
2
C BUS Serial EEPROMs
BR24G□
□□
-3A Series
□
BR24G01-3A, BR24G02-3A, BR24G04-3A, BR24G08-3A, BR24G16-3A, BR24G32-3A,
BR24G64-3A, BR24G128-3A, BR24G256-3A, BR24G512-3A, BR24G1M-3A
●Description
2
BR24G□□□-3A series is a serial EEPROM of I C BUS interface method
●Features
・
All controls available by 2 ports of serial clock(SCL) and serial data(SDA)
・
Other devices than EEPROM can be connected to the same port, saving microcontroller port
・
1.7V½5.5V single power source action most suitable for battery use
・
1.7V½5.5Vwide limit of action voltage, possible 1MHz action
・
Page write mode useful for initial value write at factory shipment
・
Auto erase and auto end function at data write
・
Low current consumption
・
Write mistake prevention function
Write (write protect) function added
Write mistake prevention function at low voltage
・
DIP-T8/SOP8/SOP-J8/SSOP-B8/TSSOP-B8/TSSOP-B8J/MSOP8/VSON008X2030 various package
・
Data rewrite up to 1,000,000 times
・
Data kept for 40 years
・
Noise filter built in SCL / SDA terminal
・
Shipment data all address FFh
●BR24G
series
Capacity Bit format
1Kbit
2Kbit
4Kbit
8Kbit
16Kbit
32Kbit
64Kbit
128Kbit
256Kbit
512Kbit
1024Kbit
128×8
256×8
512×8
1K×8
2K×8
4K×8
8K×8
16K×8
32K×8
64K×8
128K×8
Type
BR24G01-3A
BR24G02-3A
BR24G04-3A
BR24G08-3A
BR24G16-3A
BR24G32-3A
BR24G64-3A
BR24G128-3A
BR24G256-3A
BR24G512-3A
BR24G1M-3A
Power source
Voltage
DIP-T8
SOP8
SOP-J8
SSOP-B8
TSSOP-B8
TSSOP-B8J
MSOP8
VSON008
X2030
1.7½5.5V
1.7½5.5V
1.7½5.5V
1.7½5.5V
1.7½5.5V
1.7½5.5V
1.7½5.5V
1.7½5.5V
1.7½5.5V
1.7½5.5V
1.7½5.5V
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:Developing
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
2/20
2012.2 - Rev.C
BR24G□□□
□□□-3A
Series
□□□
●Absolute
maximum ratings (Ta=25℃)
Parameter
Impressed voltage
symbol
V
CC
450 (SOP8)
Limits
-0.3½+6.5
*1
*2
*3
Technical Note
●Memory
cell characteristics (Ta=25℃, Vcc=1.7½5.5V)
Unit
V
Parameter
Number of data rewrite times
Data hold years
*1
*1
Limits
Min.
1,000,000
40
*1
Typ.
-
-
Max
-
-
Unit
Times
Years
450 (SOP-J8)
Permissible
dissipation
300 (SSOP-B8)
Pd
330 (TSSOP-B8)
*4
310 (TSSOP-B8J)
*5
310 (MSOP8)
*6
mW
Not 100% TESTED
300 (VSON008X2030)
*7
800 (DIP-T8)
*8
Storage temperature range
Action temperature range
Terminal voltage
Tstg
Topr
‐
-65½+150
-40½+85
-0.3½Vcc+1.0
*9
℃
℃
V
●Recommended
operating conditions
Parameter
Power source voltage
Input voltage
Symbol
Vcc
V
IN
Limits
1.7½5.5
0½Vcc
V
Unit
Junction Temperature
*10
Tjmax
150
℃
When using at Ta=25℃ or higher, 8.0mW(*8), 4.5mW(*1,*2),
3.0mW(*3,*7), 3.3mW(*4), 3.1mW(*5, *6) to be reduced per 1℃.
*9 The Max value of Terminal Voltage is not over 6.5V. When the pulse width is 50ns or less,
the Min value of Terminal Voltage is not under -1.0V. (BR24G16/32/64/128/256/512/1M-3A)
the Min value of Terminal Voltage is not under -0.8V. (BR24G01/02/04/08-3A)
*10 Junction temperature at the storage condition.
●Electrical
characteristics
(Unless otherwise specified, Ta=-40½+85℃、VCC=1.7½5.5V)
Parameter
“H” input voltage 1
“L” input voltage 1
“L” output voltage 1
“L” output voltage 2
Input leak current
Output leak current
Symbol
V
IH1
V
IL1
V
OL1
V
OL2
I
LI
I
LO
◇
AC OPERATING CHARACTERISTICS
(Unless otherwise specified, Ta=-40½+85℃, VCC=1.7½5.5V)
Parameter
SCL frequency
Data clock “HIGH“ time
Symbol
Min.
fSCL
tHIGH
tLOW
*1
*1
*1
Limits
Min.
0.7Vcc
-0.3
*1
-
-
-1
-1
-
Typ.
-
-
-
-
-
-
-
Max.
Vcc+1.0
0.3Vcc
0.4
0.2
1
1
2.0
Limit
Typ.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max.
1000
-
-
0.12
0.12
0.12
-
-
-
-
0.45
-
-
-
5
0.05
-
-
-
-
0.3
0.5
-
-
-
0.25
0.25
0
50
0.05
0.05
0.25
0.5
-
-
1.0
0.1
1.0
Unit
V
V
V
V
µA
µA
mA
Conditions
Unit
kHz
μs
μs
μs
μs
μs
μs
μs
μs
ns
μs
μs
μs
μs
ms
μs
μs
μs
μs
I
OL
=3.0mA, 2.5V≦Vcc≦5.5V (SDA)
I
OL
=0.7mA, 1.7V≦Vcc<2.5V (SDA)
V
IN
=0½Vcc
V
OUT
=0½Vcc (SDA)
Vcc=5.5V,f
SCL
=400kHz, t
WR
=5ms,
Byte write, Page write
BR24G01/02/04/08/16/32/64-3A
Vcc=5.5V,f
SCL
=400kHz, t
WR
=5ms,
Data clock “LOW“ time
SDA and SCL rise time
SDA and SCL fall time
SDA (OUT) fall time
Start condition hold time
Start condition setup time
Input data hold time
Input data setup time
Output data delay time
Output data hold time
Stop condition setup time
Bus release time before transfer start
Internal write cycle time
Noise removal valid period (SDA, SCL terminal)
WP hold time
WP setup time
WP valid time
tR
tF1
tF2
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tPD
tDH
tSU:STO
tBUF
tWR
tI
tHD:WP
tSU:WP
tHIGH:WP
I
CC1
-
-
2.5
mA
Byte write, Page write
BR24G128/256-3A
Vcc=5.5V,f
SCL
=400kHz, t
WR
=5ms,
-
Current consumption
at action
-
I
CC2
-
-
4.5
mA
Byte write, Page write
BR24G512/1M-3A
Vcc=5.5V,f
SCL
=1MHz
-
0.5
*1
mA
Random read, current read,
sequential read
BR24G01/02/04/08/16/32/64-3A
Vcc=5.5V,f
SCL
=1MHz
-
2.0
mA
Random read, current read,
sequential read
BR24G128/256/512/1M-3A
Vcc=5.5V, SDA・SCL=Vcc
*1 Not 100% TESTED.
●AC
TIMING CHARACTERISTICS CONDITION
Parameter
Load Capacitance
SDA and SCL rise time
SDA and SCL fall time
Input Data Level
Input/Output Data Timing Refence Level
Symbol
CL
tR
tF1
VIL/VIH
-
Condition
100
20
20
0.2Vcc/0.8Vcc
0.3Vcc/0.7Vcc
Unit
pF
ns
ns
V
V
-
Standby current
I
SB
-
-
2.0
µA
A0,A1,A2=GND,WP=GND
BR24G01/02/04/08/16/32/64/128/256-3A
Vcc=5.5V, SDA・SCL=Vcc
-
3.0
µA
A0,A1,A2=GND,WP=GND
BR24G512/1M-3A
○Radiation
resistance design is not made.
*1 When the pulse width is 50ns or less, it is -1.0V. (BR24G16/32/64/128/256/512/1M-3A)
When the pulse width is 50ns or less, it is -0.8V. (BR24G01/02/04/08-3A)
●Sync
data input / output timing
tR
SCL
70%
30%
70% 70%
30%
tF1
tHIGH
70%
30%
70%
30%
70%
tHD:STA
tSU:DAT
70%
70%
30%
70%
tLOW
tHD:DAT
70%
30%
DATA(1)
D1
D0
ACK
DATA(n)
ACK
70%
SDA
(input)
tBUF
tPD
70%
30%
tDH
70%
30%
30%
tWR
30%
30%
SDA
(output)
tF2
○
Input read at the rise edge of SCL
○
Data output in sync with the fall of SCL
tSU:WP
tHD:WP
STOP CONDITION
Fig.1-(a) Sync data input / output timing
70%
70%
70%
Fig.1-(d) WP timing at write execution
tSU:STA
70%
30%
tHD:STA
tSU:STO
DATA(1)
D1
30%
DATA(n)
ACK
tHIGH:WP
70%
70%
D0
ACK
70%
tWR
START CONDITION
STOP CONDITION
Fig.1-(b) Start-stop bit timing
D0
write data
(n-th address)
ACK
70%
70%
Fig.1-(e) WP timing at write cancel
tWR
STOP CONDITION
START CONDITION
Fig.1-(c) Write cycle timing
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© 2012 ROHM Co., Ltd. All rights reserved.
3/20
2012.2 - Rev.C
BR24G□□□
□□□-3A
Series
□□□
●Block
diagram
*2
Technical Note
A0
1
*1
1Kbit
½
1024 Kbit
EEPROM array
8bit
8
Vcc
A0
1
BR24G 01-3A
BR 24G02-3A
BR 24G04-3A
BR 24G08-3A
BR 24G16-3A
BR 24G32-3A
BR 24G 64-3A
BR24G128-3A
BR 24G 256 -3A
BR24G 512 -3A
BR24G 1M -3A
8
Vcc
*1
7bit
*2
A1
2
Address
decoder
8bit
9 bit
10 bit
11bit
12 bit
13bit
14bit
15bit
16bit
17bit
Word
address register
Data
register
A1
7
WP
A2
6
SCL
GND
5
SDA
2
7
WP
3
6
SCL
START
*2
STOP
A2
3
Control circuit
ACK
4
5
SDA
GND
*
4
High voltage
generating circuit
Power source
voltage detection
1
7bit: BR24G01-3A
8bit: BR24G02-3A
9bit: BR24G04-3A
10bit: BR24G08-3A
11bit: BR24G16-3A
12bit: BR24G32-3A
13bit: BR24G64-3A
14bit: BR24G128-3A
15bit: BR24G256-3A
16bit: BR24G512-3A
17bit: BR24G1M-3A
*2 A0= Don't use : BR24G04/1M-3A
A0, A1=Don't use : BR24G08-3A
A0, A1, A2=Don't use : BR24G16-3A
Fig.2
Block diagram
●Pin
assignment and description
Terminal
Name
A0
A1
A2
GND
SDA
SCL
WP
Vcc
Input/
Output
Input
Input
Input
-
Input/
output
Input
Input
-
Slave address setting
Slave address setting
Slave address setting
Don’t use*
Don’t use*
Don’t use*
Slave address setting
Slave address setting
Slave address setting
Don’t use*
BR24G01-3A
BR24G02-3A
BR24G04-3A
BR24G08-3A
BR24G16-3A
BR24G32/64/128/256/512-3A
BR24G1M-3A
Reference voltage of all input / output, 0V
Serial data input serial data output
Serial clock input
Write protect terminal
Connect the power source.
*Pins
not used as device address may be set to any of ‘H’, 'L', and 'Hi-Z'.
●Characteristic
data (The following values are Typ. ones.)
6
6
1
L OUTPUT VOLTAGE : V
OL1
(V)
H INPUT VOLTAGE : V
IH1
(V)
L INPUT VOLTAGE : V
IL1
(V)
5
4
3
2
1
0
0
Ta=-40℃
Ta=25℃
Ta=85℃
5
4
3
2
1
Ta=-40℃
Ta=25℃
Ta=85℃
0.8
0.6
0.4
0.2
0
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
SPEC
SPEC
0
0
1
2
3
4
5
6
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
6
0
1
SUPPLY VOLTAGE : Vcc(V)
2
3
4
5
L OUTPUT CURRENT : I
OL
(mA)
6
Fig.3 'H' input voltage V
IH1
(A0,A1,A2,SCL,SDA,WP)
1
L OUTPUT VOLTAGE : V
OL2
(V)
0.8
0.6
1.2
Fig.4 'L' input voltage V
IL1
(A0,A1,A2,SCL,SDA,WP)
1.2
OUTPUT LEAK CURRENT : I
LO
(uA)
Fig.5 'L' output voltage V
OL1
-I
OL
(Vcc=1.7V)
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
0.4
0.2
0
0
1
2
3
4
5
6
L OUTPUT CURRENT : I
OL
(mA)
INPUT LEAK CURRENT : I
LI
(uA)
1
0.8
0.6
0.4
0.2
0
0
1
2
3
4
5
6
SUPPLYVOLTAGE : Vcc(V)
SPEC
1
0.8
0.6
0.4
0.2
0
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
6
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
Fig.6 'L' output voltage V
OL2
-I
OL
(Vcc=2.5V)
Fig.7 Input leak current I
LI
(A0,A1,A2,SCL,WP)
Fig.8 Output leak current I
LO
(SDA)
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© 2012 ROHM Co., Ltd. All rights reserved.
4/20
2012.2 - Rev.C
BR24G□□□
□□□-3A
Series
□□□
●Characteristic
data (The following values are Typ. ones.)
Technical Note
2.5
3.5
6
5
SPEC
CURRENT CONSUMPTION
AT WRITING : Icc1(mA)
2
3
2.5
SPEC
CURRENT CONSUMPTION
AT WRITING : Icc1(mA)
CURRENT CONSUMPTION
AT WRITING : Icc1(mA)
1.5
2
1.5
1
0.5
0
1
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
4
3
2
1
0
0
The plan for
inserting data.
(BR24G512/1M-3A)
0.5
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
1
2
3
4
5
6
SUPPLY VOLTAGE : Vcc(V)
SUPPLY VOLTAGE : Vcc(V)
SUPPLY VOLTAGE : Vcc(V)
Fig.9 Current consumption at WRITE operation I
CC
1
(fscl=1MHz BR24G01/02/04/08/16/32/64-3A)
Fig.10 Current consumption at WRITE operation Icc1
(fscl=1MHz BR24G128/256-3A)
Fig.11 Current consumption at WRITE operation Icc1
(fscl=1MHz BR24G512/1M-3A)
2.5
0.6
0.5
0.6
0.5
0.4
0.3
0.2
0.1
CURRENT CONSUMPTION
AT READING : Icc2(mA)
0.4
0.3
0.2
0.1
0
0
STANBY CURRENT : I
SB
(uA)
CURRENT CONSUMPTION
AT READING : Icc2(mA)
The plan for
inserting data.
(BR24G01/02/08/16/
32/64-3A
)
The plan for
inserting data.
(BR24G128/256/512/
1M-3A)
2
SPEC
1.5
Ta=-40℃
Ta=25℃
Ta=85℃
1
0.5
1
2
3
4
5
6
0
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
6
0
0
1
2
3
4
5
6
SUPPLY VOLTAGE : Vcc(V)
SUPPLY VOLTAGE : Vcc(V)
Fig.12 Current consumption at READ operation I
CC
2
(fscl=1MHz BR24G01/02/04/08/16/32/64/-3A)
2.5
10000
Fig.13 Current consumption at READ operation I
CC
2
(fscl=1MHz BR24G128/256/512/1M-W)
1
Fig.14 Standby operation I
SB
(BR24G01/02/04/08/16/32/64/128/256-3A)
STANBY CURRENT : I
SB
(uA)
SCL FREQUENCY : f½½½(½HZ)
DATA CLK H TIME : t
HIGH
(us)
2
1.5
The plan for
inserting data.
(BR24G512/1M-3A)
1000
100
The plan for
inserting data.
0.8
0.6
The plan for
inserting data.
1
10
0.4
0.5
1
0.2
0
0
1
2
3
4
5
6
SUPPLY VOLTAGE : Vcc(V)
0.1
0
1
2
3
4
5
6
SUPPLY VOLTAGE : Vcc(V)
0
0
1
2
3
4
5
6
SUPPLY VOLTAGE : Vcc(V)
Fig.15 Standby operation I
SB
(BR24G512/1M-3A)
START CONDITION HOLD TIME : t
HD : STA
(us)
Fig.16 SCL frequency f
SCL
1
Fig.17 Data clock High Period t
HIGH
1.1
1.5
DATA CLK L TIME : tLOW(us)
START CONDITION
SET UP TIME : tSU:STA(us)
1.2
The plan for
inserting data.
0.8
The plan for
inserting data.
0.9
0.7
0.5
0.3
0.1
-0.1
The plan for
inserting data.
0.9
0.6
0.6
0.4
0.3
0.2
0
0
1
2
3
4
5
6
SUPPLY VOLTAGE : Vcc(V)
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
SUPPLY VOLTAGE : Vcc(V)
SUPPLY VOLTAGE : Vcc(V)
Fig.18 Data clock Low Period t
LOW
50
Fig.19 Start Condition Hold Time t
HD : STA
50
Fig.20 Start Condition Setup Time t
SU : STA
INPUT DATA HOLD TIME : t
HD :DAT
(ns)
INPUT DATA HOLD TIME : t
HD: STA
(ns)
300
0
-50
-100
-150
-200
0
The plan for
inserting data.
0
-50
-100
-150
-200
0
The plan for
inserting data.
INPUT DATA SET UP TIME : t
SU: DAT
(ns)
200
100
0
-100
-200
0
The plan for
inserting data.
1
2
3
4
5
6
1
2
3
4
5
6
1
2
3
4
5
6
SUPPLY VOLTAGE : Vcc(V)
SUPPLY VOLTAGE : Vcc(V)
SUPPLY VOLTAGE : Vcc(V)
Fig.21 Input Data Hold Time t
HD : DAT
(HIGH)
Fig.22 Input Data Hold Time
½
HD : DAT
(LOW)
Fig.23 Input Data Setup Time
½
SU: DAT
(HIGH)
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2012.2 - Rev.C