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-1-
K4B1G0446E
K4B1G0846E
K4B1G1646E
datasheet
History
- First release
- Corrected Typo.
- ADD IDDQ2NT, IDDQ4R, IDD8 Specification
- Corrected AC Timing Table
- Added IDD Current Specification for DDR3-1600
- Added Layout and Corrected Typo.
Draft Date
Feb. 2009
June. 2009
July. 2009
Sep. 2009
Oct. 2009
Nov. 2009
Rev. 1.4
DDR3 SDRAM
Revision History
Revision No.
1.0
1.01
1.1
1.2
1.3
1.4
Remark
-
-
-
-
-
-
Editor
S.H.KiM
S.H.KiM
S.H.KiM
S.H.KiM
S.H.KiM
S.H.KiM
-2-
K4B1G0446E
K4B1G0846E
K4B1G1646E
datasheet
Rev. 1.4
DDR3 SDRAM
Table Of Contents
1Gb E-die DDR3 SDRAM
1. Ordering Information ..................................................................................................................................................... 5
6. Absolute Maximum Ratings .......................................................................................................................................... 13
6.1 Absolute Maximum DC Ratings............................................................................................................................... 13
6.2 DRAM Component Operating Temperature Range ................................................................................................ 13
7. AC & DC Operating Conditions..................................................................................................................................... 13
7.1 Recommended DC operating Conditions (SSTL_1.5)............................................................................................. 13
8. AC & DC Input Measurement Levels ............................................................................................................................ 14
8.1 AC & DC Logic input levels for single-ended signals .............................................................................................. 14
8.3 AC & DC Logic Input Levels for Differential Signals............................................................................................... 16
8.3.2. Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS) .................................................. 16
8.3.3. Single-ended requirements for differential signals ........................................................................................... 17
8.4 Differential Input Cross Point Voltage...................................................................................................................... 18
8.5 Slew rate definition for Differential Input Signals ..................................................................................................... 18
8.6 Slew rate definitions for Differential Input Signals ................................................................................................... 18
9. AC & DC Output Measurement Levels ........................................................................................................................ 19
9.1 Single-ended AC & DC Output Levels..................................................................................................................... 19
9.2 Differential AC & DC Output Levels......................................................................................................................... 19
9.6.1. Address and Control Overshoot and Undershoot specifications...................................................................... 21
9.6.2. Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications ...................................................... 21
9.7 34ohm Output Driver DC Electrical Characteristics................................................................................................. 22
9.7.1. Output Drive Temperature and Voltage Sensitivity .......................................................................................... 23
9.8 On-Die Termination (ODT) Levels and I-V Characteristics ..................................................................................... 23
9.8.1. ODT DC Electrical Characteristics ................................................................................................................... 24
9.8.2. ODT Temperature and Voltage sensitivity ...................................................................................................... 25
9.9.1. Test Load for ODT Timings.............................................................................................................................. 26
13.1.1. Definition for tCK(avg).................................................................................................................................... 41
13.1.2. Definition for tCK(abs).................................................................................................................................... 41
13.1.3. Definition for tCH(avg) and tCL(avg) .............................................................................................................. 41
13.1.4. Definition for note for tJIT(per), tJIT(per, Ick) ................................................................................................. 41
13.1.5. Definition for tJIT(cc), tJIT(cc, Ick) ................................................................................................................. 41
13.1.6. Definition for tERR(nper)................................................................................................................................ 41
13.2 Refresh Parameters by Device Density42
-3-
K4B1G0446E
K4B1G0846E
K4B1G1646E
datasheet
Rev. 1.4
DDR3 SDRAM
13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 42
13.3.1. Speed Bin Table Notes .................................................................................................................................. 45
14. Timing Parameters by Speed Grade .......................................................................................................................... 46
14.3 Address/Command Setup, Hold and Derating : .................................................................................................... 51
14.4 Data Setup, Hold and Slew Rate Derating : .......................................................................................................... 57
• Programmable Additive Latency: 0, CL-2 or CL-1 clock
• Programmable CAS Write Latency (CWL) = 5 (DDR3-800), 6
(DDR3-1066), 7 (DDR3-1333) and 8 (DDR3-1600)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with starting
address “000” only), 4 with tCCD = 4 which does not allow seamless
read or write [either On the fly using A12 or MRS]
• Bi-directional Differential Data-Strobe
• Internal(self) calibration : Internal self calibration through ZQ pin
(RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than T
CASE
85°C, 3.9us at
85°C < T
CASE
< 95
°C
• Asynchronous Reset
• Package : 78 balls FBGA - x4/x8
96 balls FBGA - x16
• All of Lead-Free products are compliant for RoHS
• All of products are Halogen-free
The 1Gb DDR3 SDRAM E-die is organized as a 32Mbit x 4 I/Os x 8banks,
16Mbit x 8 I/Os x 8banks or 8Mbit x 16 I/Os x 8 banks device. This synchro-
nous device achieves high speed double-data-rate transfer rates of up to
1600Mb/sec/pin (DDR3-1600) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM fea-
tures such as posted CAS, Programmable CWL, Internal (Self) Calibration,
On Die Termination using ODT pin and Asynchronous Reset .
All of the control and address inputs are synchronized with a pair of exter-
nally supplied differential clocks. Inputs are latched at the crosspoint of dif-
ferential clocks (CK rising and CK falling). All I/Os are synchronized with a
pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-
ion. The address bus is used to convey row, column, and bank address
information in a RAS/CAS multiplexing style. The DDR3 device operates
with a single 1.5V ± 0.075V power supply and 1.5V ± 0.075V V
DDQ
.
The 1Gb DDR3 E-die device is available in 78ball FBGAs(x4/x8) and 96ball
FBGA(x16)
NOTE
: The functionality described and the timing specifications included in this data
sheet are for the DLL Enabled mode of operation.
NOTE
: This data sheet is an abstract of full DDR3 specification and does not cover the common features which are described in “DDR3 SDRAM Device Operation & Timing
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