K4B2G0446C-HYF70 datasheet, PDF

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K4B2G0446C-HYF70: DescriptionDDR DRAM, 512MX4, CMOS, PBGA78, HALOGEN FREE AND ROHS COMPLIANT, FBGA-78; Categorystorage storage; File Size2MB，61 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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K4B2G0446C-HYF70 Overview

DDR DRAM, 512MX4, CMOS, PBGA78, HALOGEN FREE AND ROHS COMPLIANT, FBGA-78

K4B2G0446C-HYF70 Parametric

Parameter Name	Attribute value
Maker	SAMSUNG
Parts packaging code	BGA
package instruction	TFBGA,
Contacts	78
Reach Compliance Code	unknow
ECCN code	EAR99
Other features	AUTO/SELF REFRESH
Spare memory width	8
JESD-30 code	R-PBGA-B78
length	11 mm
memory density	2147483648 bi
Memory IC Type	DDR DRAM
memory width	4
Number of functions	1
Number of ports	1
Number of terminals	78
word count	536870912 words
character code	512000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	95 °C
Minimum operating temperature
organize	512MX4
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Certification status	Not Qualified
Maximum seat height	1.2 mm
self refresh	YES
Maximum supply voltage (Vsup)	1.575 V
Minimum supply voltage (Vsup)	1.425 V
Nominal supply voltage (Vsup)	1.5 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
width	7.5 mm

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Rev. 1.02, Dec. 2009

K4B2G0446C

K4B2G0846C

2Gb C-die DDR3L SDRAM

78FBGA with Lead-Free & Halogen-Free

(RoHS compliant)

datasheet

SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND

SPECIFICATIONS WITHOUT NOTICE.

Products and specifications discussed herein are for reference purposes only. All information discussed

herein is provided on an "AS IS" basis, without warranties of any kind.

This document and all information discussed herein remain the sole and exclusive property of Samsung

Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property

right is granted by one party to the other party under this document, by implication, estoppel or other-

wise.

Samsung products are not intended for use in life support, critical care, medical, safety equipment, or

similar applications where product failure could result in loss of life or personal or physical harm, or any

military or defense application, or any governmental procurement to which special terms or provisions

may apply.

For updates or additional information about Samsung products, contact your nearest Samsung office.

All brand names, trademarks and registered trademarks belong to their respective owners.

ⓒ

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K4B2G0446C

K4B2G0846C

datasheet

Rev. 1.02

DDR3L SDRAM

Table Of Contents

2Gb C-die DDR3L SDRAM

1. Ordering Information ..................................................................................................................................................... 5

2. Key Features................................................................................................................................................................. 5

3. Package pinout/Mechanical Dimension & Addressing.................................................................................................. 6

3.1 x4 Package Pinout (Top view) : 78ball FBGA Package .......................................................................................... 6

3.2 x8 Package Pinout (Top view) : 78ball FBGA Package .......................................................................................... 7

3.3 FBGA Package Dimension (x4/x8) .......................................................................................................................... 8

4. Input/Output Functional Description.............................................................................................................................. 9

5. DDR3 SDRAM Addressing ........................................................................................................................................... 10

6. Absolute Maximum Ratings .......................................................................................................................................... 11

6.1 Absolute Maximum DC Ratings............................................................................................................................... 11

6.2 DRAM Component Operating Temperature Range ................................................................................................ 11

7. AC & DC Operating Conditions..................................................................................................................................... 11

7.1 Recommended DC operating Conditions (SSTL_1.5)............................................................................................. 11

8. AC & DC Input Measurement Levels ............................................................................................................................ 12

8.1 AC & DC Logic input levels for single-ended signals .............................................................................................. 12

8.2 V

REF

Tolerances...................................................................................................................................................... 13

8.3 AC & DC Logic Input Levels for Differential Signals ................................................................................................ 14

8.3.1. Differential signals definition ............................................................................................................................ 14

8.3.2. Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS) .................................................. 14

8.3.3. Single-ended requirements for differential signals ........................................................................................... 15

8.4 Differential Input Cross Point Voltage...................................................................................................................... 16

8.5 Slew rate definition for Differential Input Signals ..................................................................................................... 16

8.6 Slew rate definitions for Differential Input Signals ................................................................................................... 16

9. AC & DC Output Measurement Levels ......................................................................................................................... 17

9.1 Single-ended AC & DC Output Levels..................................................................................................................... 17

9.2 Differential AC & DC Output Levels......................................................................................................................... 17

9.3 Single-ended Output Slew Rate .............................................................................................................................. 17

9.4 Differential Output Slew Rate .................................................................................................................................. 18

9.5 Reference Load for AC Timing and Output Slew Rate ............................................................................................ 18

9.6 Overshoot/Undershoot Specification ....................................................................................................................... 19

9.6.1. Address and Control Overshoot and Undershoot specifications...................................................................... 19

9.6.2. Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications ...................................................... 20

9.7 34ohm Output Driver DC Electrical Characteristics................................................................................................. 20

9.7.1. Output Drive Temperature and Voltage Sensitivity .......................................................................................... 22

9.8 On-Die Termination (ODT) Levels and I-V Characteristics ..................................................................................... 22

9.8.1. ODT DC Electrical Characteristics ................................................................................................................... 23

9.8.2. ODT Temperature and Voltage sensitivity ...................................................................................................... 25

9.9 ODT Timing Definitions ........................................................................................................................................... 26

9.9.1. Test Load for ODT Timings .............................................................................................................................. 26

9.9.2. ODT Timing Definitions .................................................................................................................................... 26

10. IDD Current Measure Method ..................................................................................................................................... 29

10.1 IDD Measurement Conditions ............................................................................................................................... 29

11. 2Gb DDR3 SDRAM C-die IDD Specification Table .................................................................................................... 38

12. Input/Output Capacitance ........................................................................................................................................... 39

13. Electrical Characteristics and AC timing for DDR3-800 to DDR3-1600 ...................................................................... 40

13.1 Clock Specification ................................................................................................................................................ 40

13.1.1. Definition for tCK(avg).................................................................................................................................... 40

13.1.2. Definition for tCK(abs).................................................................................................................................... 40

13.1.3. Definition for tCH(avg) and tCL(avg) .............................................................................................................. 40

13.1.4. Definition for note for tJIT(per), tJIT(per, Ick) ................................................................................................. 40

13.1.5. Definition for tJIT(cc), tJIT(cc, Ick) ................................................................................................................. 40

13.1.6. Definition for tERR(nper)................................................................................................................................ 40

13.2 Refresh Parameters by Device Density................................................................................................................. 41

13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 41

13.3.1. Speed Bin Table Notes44

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K4B2G0446C-HYF70 Related Products

	K4B2G0446C-HYF70	K4B2G0446C-HYF80	K4B2G0846C-HYF80	K4B2G0846C-HYH90	K4B2G0446C-HYK00	K4B2G0446C-HYH90	K4B2G0846C-HYK00
Description	DDR DRAM, 512MX4, CMOS, PBGA78, HALOGEN FREE AND ROHS COMPLIANT, FBGA-78	DDR DRAM, 512MX4, CMOS, PBGA78, HALOGEN FREE AND ROHS COMPLIANT, FBGA-78	DDR DRAM, 256MX8, CMOS, PBGA78, HALOGEN FREE AND ROHS COMPLIANT, FBGA-78	DDR DRAM, 256MX8, CMOS, PBGA78, HALOGEN FREE AND ROHS COMPLIANT, FBGA-78	DDR DRAM, 512MX4, CMOS, PBGA78, HALOGEN FREE AND ROHS COMPLIANT, FBGA-78	DDR DRAM, 512MX4, 0.225ns, CMOS, PBGA78, HALOGEN FREE AND ROHS COMPLIANT, FBGA-78	DDR DRAM, 256MX8, CMOS, PBGA78, HALOGEN FREE AND ROHS COMPLIANT, FBGA-78
Parts packaging code	BGA	BGA	BGA	BGA	BGA	BGA	BGA
package instruction	TFBGA,	TFBGA,	TFBGA,	TFBGA,	TFBGA,	TFBGA,	TFBGA,
Contacts	78	78	78	78	78	78	78
Reach Compliance Code	unknow	compliant	compliant	compliant	compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
Spare memory width	8	8	4	4	8	8	4
JESD-30 code	R-PBGA-B78	R-PBGA-B78	R-PBGA-B78	R-PBGA-B78	R-PBGA-B78	R-PBGA-B78	R-PBGA-B78
length	11 mm	11 mm	11 mm	11 mm	11 mm	11 mm	11 mm
memory density	2147483648 bi	2147483648 bit	2147483648 bit	2147483648 bit	2147483648 bit	2147483648 bit	2147483648 bit
Memory IC Type	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM
memory width	4	4	8	8	4	4	8
Number of functions	1	1	1	1	1	1	1
Number of ports	1	1	1	1	1	1	1
Number of terminals	78	78	78	78	78	78	78
word count	536870912 words	536870912 words	268435456 words	268435456 words	536870912 words	536870912 words	268435456 words
character code	512000000	512000000	256000000	256000000	512000000	512000000	256000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	95 °C	95 °C	95 °C	95 °C	95 °C	95 °C	95 °C
organize	512MX4	512MX4	256MX8	256MX8	512MX4	512MX4	256MX8
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm
self refresh	YES	YES	YES	YES	YES	YES	YES
Maximum supply voltage (Vsup)	1.575 V	1.575 V	1.575 V	1.575 V	1.575 V	1.575 V	1.575 V
Minimum supply voltage (Vsup)	1.425 V	1.425 V	1.425 V	1.425 V	1.425 V	1.425 V	1.425 V
Nominal supply voltage (Vsup)	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V
surface mount	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
width	7.5 mm	7.5 mm	7.5 mm	7.5 mm	7.5 mm	7.5 mm	7.5 mm
Maker	SAMSUNG	SAMSUNG	-	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG

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