K4T51083QG-HCD50 datasheet, PDF

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K4T51083QG-HCD50: DescriptionDDR DRAM, 64MX8, 0.5ns, CMOS, PBGA60, ROHS COMPLIANT, FBGA-60; Categorystorage storage; File Size536KB，26 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/; Environmental Compliance

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K4T51083QG-HCD50 Overview

DDR DRAM, 64MX8, 0.5ns, CMOS, PBGA60, ROHS COMPLIANT, FBGA-60

K4T51083QG-HCD50 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	SAMSUNG
Parts packaging code	BGA
package instruction	TFBGA, BGA60,9X11,32
Contacts	60
Reach Compliance Code	unknow
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	0.5 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	267 MHz
I/O type	COMMON
interleaved burst length	4,8
JESD-30 code	R-PBGA-B60
length	9.5 mm
memory density	536870912 bi
Memory IC Type	DDR DRAM
memory width	8
Number of functions	1
Number of ports	1
Number of terminals	60
word count	67108864 words
character code	64000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	95 °C
Minimum operating temperature
organize	64MX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Encapsulate equivalent code	BGA60,9X11,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.8 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	4,8
Maximum standby current	0.0045 A
Maximum slew rate	0.175 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.5 mm

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RDIMM

DDR2 SDRAM

DDR2 Registered SDRAM MODULE

240pin Registered Module based on 512Mb E-die

72-bit ECC

60FBGA with Lead-Free

(RoHS compliant)

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE

CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-

WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-

OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT

GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure could result in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

1 of 26

Rev. 1.4 August 2008

RDIMM

Table of Contents

DDR2 SDRAM

1.0 DDR2 Registered DIMM Ordering Information ..........................................................................4

2.0 Features ........................................................................................................................................4

3.0 Address Configuration ................................................................................................................4

4.0 Pin Configurations (Front side/Back side) ................................................................................5

5.0 Pin Description ............................................................................................................................5

6.0 Input/Output Functional Description .........................................................................................6

7.0 Functional Block Diagram ...........................................................................................................7

7.1 512MB, 64Mx72 Module - M393T6553EZ3/M393T6553EZA

.................................................................7

7.2 1GB, 128Mx72 Module - M393T2953EZ3/M393T2953EZA

....................................................................8

7.3 1GB, 128Mx72 Module - M393T2950EZ3/M393T2950EZA

...................................................................9

7.4 2GB, 256Mx72 Module - M393T5750EZ3/M393T5750EZA

..................................................................10

8.0 Absolute Maximum DC Ratings ................................................................................................11

9.0 AC & DC Operating Conditions ................................................................................................11

9.1 Recommended DC Operating Conditions (SSTL - 1.8)

.....................................................................11

9.2 Operating Temperature Condition

................................................................................................12

9.3 Input DC Logic Level

..................................................................................................................12

9.4 Input AC Logic Level

..................................................................................................................12

9.5 AC Input Test Conditions

............................................................................................................12

10.0 IDD Specification Parameters Definition ...............................................................................13

11.0 Operating Current Table : .......................................................................................................14

11.1 M393T6553EZ3 / M393T6553EZA : 512MB(64Mx8 *9) Module

.........................................................14

11.2 M393T6553EZ3 / M393T6553EZA : 512MB(64Mx8 *9) Module

.........................................................14

11.3 M393T2953EZ3 / M393T2953EZA : 1GB(64Mx8 *18) Module

...........................................................15

11.4 M393T2953EZ3 / M393T2953EZA : 1GB(64Mx8 *18) Module

...........................................................15

11.5 M393T2950EZ3 / M393T2950EZA : 1GB(128Mx4 *18) Module

.........................................................16

11.6 M393T2950EZ3 / M393T2950EZA : 1GB(128Mx4 *18) Module

.........................................................16

11.7 M393T5750EZ3 / M393T5750EZA : 2GB(128Mx4 *36) Module

.........................................................17

11.8 M393T5750EZ3 / M393T5750EZA : 2GB(128Mx4 *36) Module

.........................................................17

12.0 Input/Output Capacitance .......................................................................................................18

13.0 Electrical Characteristics & AC Timing for DDR2-800/667/533/400 .....................................18

13.1 Refresh Parameters by Device Density

........................................................................................18

13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin

.............................................18

13.3 Timing parameters by speed grade (DDR2-800 and DDR2-667)

.......................................................19

13.4 Timing parameters by speed grade (DDR2-533 and DDR2-400)

.......................................................21

14.0 Physical Dimensions ...............................................................................................................23

14.1 64Mbx8 based 64Mx72 Module (1 Rank)

......................................................................................23

14.2 64Mbx8/128Mbx4 based 128Mx72 Module (2/1 Ranks)

...................................................................24

14.3 128Mbx4 based 256Mx72 Module (2 Ranks

) .................................................................................25

15.0 240 Pin DDR2 Registered DIMM Clock Topology .................................................................26

2 of 26

Rev. 1.4 August 2008

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