7. SPD and Thermal Sensor for ECC UDIMMs ................................................................................................................ 7
8.1.1. DRAM Pin Wiring Mirroring .............................................................................................................................. 9
9. Function Block Diagram: ............................................................................................................................................... 10
9.1 1GB, 128Mx64 Non ECC Module (Populated as 1 rank of x8 DDR3 SDRAMs) ..................................................... 10
9.2 1GB, 128Mx72 ECC Module (Populated as 1 rank of x8 DDR3 SDRAMs) ............................................................ 11
9.3 2GB, 256Mx64 Non ECC Module (Populated as 2 ranks of x8 DDR3 SDRAMs) ................................................... 12
9.4 2GB, 256Mx72 ECC Module (Populated as 2 ranks of x8 DDR3 SDRAMs).......................................................... 13
10. Absolute Maximum Ratings ........................................................................................................................................ 14
10.1 Absolute Maximum DC Ratings............................................................................................................................. 14
10.2 DRAM Component Operating Temperature Range .............................................................................................. 14
11. AC & DC Operating Conditions................................................................................................................................... 14
11.1 Recommended DC Operating Conditions (SSTL-15)............................................................................................ 14
12. AC & DC Input Measurement Levels .......................................................................................................................... 15
12.1 AC & DC Logic Input Levels for Single-ended Signals .......................................................................................... 15
12.3 AC and DC Logic Input Levels for Differential Signals .......................................................................................... 17
12.3.2. Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS) ............................................. 17
12.3.3. Single-ended Requirements for Differential Signals ...................................................................................... 18
12.3.4. Differential Input Cross Point Voltage ............................................................................................................ 19
12.4 Slew Rate Definition for Single Ended Input Signals ............................................................................................. 19
12.5 Slew rate definition for Differential Input Signals ................................................................................................... 19
13. AC & DC Output Measurement Levels ....................................................................................................................... 20
13.1 Single Ended AC and DC Output Levels............................................................................................................... 20
13.2 Differential AC and DC Output Levels ................................................................................................................... 20
17. Electrical Characteristics and AC timing ..................................................................................................................... 27
17.1 Refresh Parameters by Device Density................................................................................................................. 27
17.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................ 27
17.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 27
17.3.1. Speed Bin Table Notes .................................................................................................................................. 31
18. Timing Parameters by Speed Grade .......................................................................................................................... 32
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ADI Reference Circuit
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