PPC405EP-3LB133C datasheet, PDF

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PPC405EP-3LB133C: DescriptionRISC Microprocessor, 32-Bit, 133.33MHz, CMOS, PBGA385, 31 X 31 MM, LEAD FREE, PLASTIC, EBGA-385; CategoryThe embedded processor and controller Microcontrollers and processors; File Size392KB，50 Pages; ManufacturerApplied Micro Circuits (MACOM); Environmental Compliance

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PPC405EP-3LB133C Overview

RISC Microprocessor, 32-Bit, 133.33MHz, CMOS, PBGA385, 31 X 31 MM, LEAD FREE, PLASTIC, EBGA-385

PPC405EP-3LB133C Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Applied Micro Circuits (MACOM)
Parts packaging code	BGA
package instruction	BGA, BGA385,23X23,50
Contacts	385
Reach Compliance Code	compli
ECCN code	3A001.A.3
Other features	ALSO REQUIRES 3.3V SUPPLY
Address bus width
bit size	32
boundary scan	YES
maximum clock frequency	100 MHz
External data bus width
Format	FIXED POINT
Integrated cache	YES
JESD-30 code	S-PBGA-B385
length	31 mm
low power mode	YES
Number of terminals	385
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA385,23X23,50
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.8,3.3 V
Certification status	Not Qualified
Maximum seat height	2.65 mm
speed	133.33 MHz
Maximum supply voltage	1.95 V
Minimum supply voltage	1.65 V
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	31 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC

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Part Number PPC405EP

Revision 1.07 – September 10, 2007

PPC405EP

PowerPC 405EP Embedded Processor

Features

•

AMCC PowerPC

405 32-bit RISC processor

core operating up to 333MHz with 16KB D-

and I-caches

PC-133 synchronous DRAM (SDRAM) inter-

face

- 32-bit interface for non-ECC applications

4KB on-chip memory (OCM)

External peripheral bus

- Flash ROM/Boot ROM interface

- Direct support for 8- or 16-bit SRAM and

external peripherals

- Up to five devices

DMA support for memory and UARTs.

- Scatter-gather chaining supported

- Four channels

PCI Revision 2.2 compliant interface (32-bit, up

to 66MHz)

Data Sheet

•

- Asynchronous PCI Bus interface

- Internal or external PCI Bus Arbiter

Two Ethernet 10/100Mbps (full-duplex) ports

with media independent interface (MII)

Programmable interrupt controller supports

seven external and 19 internal edge-triggered

or level-sensitive interrupts

Programmable timers

Software accessible event counters

Two serial ports (16750 compatible UART)

One IIC interface

General purpose I/O (GPIO) available

Supports JTAG for board level testing

Internal processor local bus (PLB) runs at

SDRAM interface frequency

Supports PowerPC processor boot from PCI

memory

Description

Designed specifically to address embedded

applications, the PowerPC 405EP (PPC405EP)

provides a high-performance, low-power solution that

interfaces to a wide range of peripherals by

incorporating on-chip power management features

and lower power dissipation requirements.

This chip contains a high-performance RISC

processor core, SDRAM controller, PCI bus interface,

Ethernet interface, control for external ROM and

peripherals, DMA with scatter-gather support, serial

ports, IIC interface, and general purpose I/O.

Technology: CMOS SA-27E, 0.18

μm

(0.11

μm

eff

)

Package: 31mm, 385-ball, enhanced plastic ball grid

array (E-PBGA)

Power (typical): 0.72W at 266MHz

AMCC

PPC405EP – PowerPC 405EP Embedded Processor

Revision 1.07 – September 10, 2007

Data Sheet

Table of Contents

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering, PVR, and JTAG Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PLB to PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

External Peripheral Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

10/100 Mbps Ethernet MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Pin Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Signal List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

AMCC

PPC405EP – PowerPC 405EP Embedded Processor

Revision 1.07 – September 10, 2007

Data Sheet

List of Figures

PPC405EP Embedded Controller Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

31mm, 385-Ball E-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5V-Tolerant Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Clocking Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Input Setup and Hold Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

List of Tables

System Memory Address Map (4GB System Memory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

DCR Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Peripheral Interface Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

I/O Specifications—Group 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

I/O Specifications—Group 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

AMCC

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