-55°C to +125°C, Single-Chip, One-Output Clock Generator
,2
The Smart Timing Choice
The Smart Timing Choice
Features
Applications
Any frequency between 1 MHz to 110 MHz accurate to 6 decimal
places of accuracy
Operating temperature from -55°C to 125°C
Excellent total frequency stability as low as ±20 ppm
Low power consumption of 3.6 mA typical at 1.8V
LVCMOS/LVTTL compatible output
5-pin SOT23-5: 2.9mm x 2.8mm
RoHS and REACH compliant, Pb-free, Halogen-free and
Antimony-free
For AEC-Q100 oscillators, refer to
SiT2024
and
SiT2025
Ruggedized equipment in harsh operating environment
Electrical Specifications
Table 1. Electrical Characteristics
[1, 2]
Parameters
Output Frequency Range
Frequency Stability
Symbol
f
F_stab
Min.
1
-20
-25
-30
-50
Operating Temperature Range
Supply Voltage
T_use
Vdd
-55
1.62
2.25
2.52
2.7
2.97
2.25
Current Consumption
Idd
–
–
–
OE Disable Current
Standby Current
I_od
I_std
–
–
–
–
–
Duty Cycle
Rise/Fall Time
DC
Tr, Tf
45
–
–
–
Output High Voltage
VOH
90%
Typ.
–
–
–
–
–
–
1.8
2.5
2.8
3.0
3.3
–
3.8
3.6
3.4
–
–
2.6
1.4
0.6
–
1.0
1.3
1
–
Max.
110
+20
+25
+30
+50
+125
1.98
2.75
3.08
3.3
3.63
3.63
4.5
4.2
4
4.4
4.1
8.5
5.5
3.5
55
2.0
2.5
2.0
–
Unit
MHz
ppm
ppm
ppm
ppm
°C
V
V
V
V
V
V
mA
mA
mA
mA
mA
A
A
A
%
ns
ns
ns
Vdd
No load condition, f = 20 MHz, Vdd = 2.8V, 3.0V, 3.3V or 2.25 to
3.63V
No load condition, f = 20 MHz, Vdd = 2.5V
No load condition, f = 20 MHz, Vdd = 1.8V
Vdd = 2.5V to 3.3V, OE = Low, Output in high Z state
Vdd = 1.8V, OE = Low, Output in high Z state
Vdd = 2.8V to 3.3V, ST = Low, Output is Weakly Pulled Down
Vdd = 2.5V, ST = Low, Output is Weakly Pulled Down
Vdd = 1.8V, ST = Low, Output is Weakly Pulled Down
All Vdds
Vdd = 2.5V, 2.8V, 3.0V or 3.3V, 20% - 80%
Vdd =1.8V, 20% - 80%
Vdd = 2.25V - 3.63V, 20% - 80%
IOH = -4 mA (Vdd = 3.0V or 3.3V)
IOH = -3 mA (Vdd = 2.8V and Vdd = 2.5V)
IOH = -2 mA (Vdd = 1.8V)
IOL = 4 mA (Vdd = 3.0V or 3.3V)
IOL = 3 mA (Vdd = 2.8V and Vdd = 2.5V)
IOL = 2 mA (Vdd = 1.8V)
Pin 3, OE or ST
Pin 3, OE or ST
Pin 3, OE logic high or logic low, or ST logic high
Pin 3, ST logic low
Condition
Refer to
Table 14
for the exact list of supported frequencies
Inclusive of Initial tolerance at 25°C, 1st year aging at 25°C, and
variations over operating temperature, rated power supply
voltage and load (15 pF ± 10%).
Frequency Range
Frequency Stability and Aging
Operating Temperature Range
Supply Voltage and Current Consumption
LVCMOS Output Characteristics
Output Low Voltage
VOL
–
–
10%
Vdd
Input Characteristics
Input High Voltage
Input Low Voltage
Input Pull-up Impedance
VIH
VIL
Z_in
70%
–
50
2
–
–
87
–
–
30%
150
–
Vdd
Vdd
k
M
SiTime Corporation
Rev. 1.0
990 Almanor Avenue, Sunnyvale, CA 94085
(408) 328-4400
www.sitime.com
Revised October 16, 2014
SiT2020
-55°C to +125°C, Single-Chip, One-Output Clock Generator
The Smart Timing Choice
The Smart Timing Choice
Table 1. Electrical Characteristics
[1, 2]
(continued)
Parameters
Startup Time
Enable/Disable Time
Resume Time
RMS Period Jitter
Peak-to-peak Period Jitter
RMS Phase Jitter (random)
Symbol
T_start
T_oe
T_resume
T_jitt
T_pk
T_phj
Min.
–
–
–
–
–
–
–
–
–
Typ.
–
–
–
1.6
1.9
12
14
0.5
1.3
Max.
5
140
5
Jitter
2.5
3
20
25
0.8
2
ps
ps
ps
ps
ps
ps
f = 75MHz, Vdd = 2.5V, 2.8V, 3.0V or 3.3V
f = 75MHz, Vdd = 1.8V
f = 75 MHz, Vdd = 2.5V, 2.8V, 3.0V or 3.3V
f = 75 MHz, Vdd = 1.8V
Integration bandwidth = 900 kHz to 7.5 MHz
Integration bandwidth = 12 kHz to 20 MHz
Unit
ms
ns
ms
Condition
Measured from the time Vdd reaches 90% of final value
f = 75 MHz. For other frequencies, T_oe = 100 ns + 3 * clock
periods
Measured from the time ST pin crosses 50% threshold
Startup and Resume Timing
Notes:
1. All electrical specifications in the above table are specified with 15 pF output load and for all Vdd(s) unless otherwise stated.
2. The typical value of any parameter in the Electrical Characteristics table is specified for the nominal value of the highest voltage option for that parameter and at
25 °C temperature.
Table 2. Pin Description
Pin
1
2
Symbol
GND
NC
Power
No Connect
Output
Enable
3
OE/ ST/NC
Standby
No Connect
4
5
VDD
OUT
Power
Output
Electrical ground
[3]
No connect
H
[4]
: specified frequency output
L: output is high impedance. Only output driver is disabled.
H or Open
[4]
: specified frequency output
L: output is low (weak pull down). Device goes to sleep mode. Supply
current reduces to I_std.
Any voltage between 0 and Vdd or Open
[4]
: Specified frequency
output. Pin 3 has no function.
Power supply voltage
[3]
Oscillator output
4
5
Functionality
Top View
OE/ST/NC NC
3
2
GND
1
VDD
OUT
Notes:
3. A capacitor of value 0.1 µF or higher between Vdd and GND is required.
4. In OE or ST mode, a pull-up resistor of 10 kΩ or less is recommended if pin 3 is not externally driven.
If pin 3 needs to be left floating, use the NC option.
Figure 1. Pin Assignments
Rev. 1.0
Page 2 of 12
www.sitime.com
SiT2020
-55°C to +125°C, Single-Chip, One-Output Clock Generator
The Smart Timing Choice
The Smart Timing Choice
N
Table 3. Absolute Maximum Limits
Attempted operation outside the absolute maximum ratings may cause permanent damage to the part. Actual performance of
the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Storage Temperature
Vdd
Electrostatic Discharge
Soldering Temperature (follow standard Pb free soldering guidelines)
Junction Temperature
[5]
Min.
-65
-0.5
–
–
–
Max.
150
4
2000
260
150
Unit
°C
V
V
°C
°C
Note:
5. Exceeding this temperature for extended period of time may damage the device.
Table 4. Thermal Consideration
[6]
Package
SOT23-5
JA
, 4 Layer Board
(°C/W)
421
JC
, Bottom
(°C/W)
175
Note:
6. Refer to JESD51 for
JA
and
JC
definitions, and reference layout used to determine the
JA
and
JC
values in the above table.
Table 5. Maximum Operating Junction Temperature
[7]
Max Operating Temperature
125°C
Maximum Operating Junction Temperature
135°C
Note:
7. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.
Table 6. Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Moisture Sensitivity Level
Condition/Test Method
MIL-STD-883F, Method 2002
MIL-STD-883F, Method 2007
JESD22, Method A104
MIL-STD-883F, Method 2003
MSL1 @ 260°C
Rev. 1.0
Page 3 of 12
www.sitime.com
SiT2020
-55°C to +125°C, Single-Chip, One-Output Clock Generator
The Smart Timing Choice
The Smart Timing Choice
Test Circuit and Waveform
[8]
Test
Point
Vout
Vdd
Tr
5
4
0.1µF
Power
Supply
Tf
15 pF
(including probe
and fixture
capacitance)
1
2
3
80% Vdd
50%
20% Vdd
High Pulse
(TH)
Low Pulse
(TL)
Period
1k
Ω
Vdd
OE/ST Function
Figure 2. Test Circuit
Note:
8. Duty Cycle is computed as Duty Cycle = TH/Period.
Figure 3. Output Waveform
Timing Diagrams
90% Vdd
Vdd
50% Vdd
Vdd
Pin 4 Voltage
T_start
No Glitch
during start up
[9]
ST Voltage
T_resume
CLK Output
CLK Output
T_start: Time to start from power-off
T_resume: Time to resume from ST
Figure 4. Startup Timing (OE/ST Mode)
u
Figure 5. Standby Resume Timing (ST Mode Only)
Vdd
50% Vdd
OE Voltage
T_oe
OE Voltage
Vdd
50% Vdd
T_oe
CLK Output
CLK Output
HZ
T_oe: Time to re-enable the clock output
T_oe: Time to put the output in High Z mode
Figure 6. OE Enable Timing (OE Mode Only)
Note:
9. SiT2020 has “no runt” pulses and “no glitch” output during startup or resume.
Figure 7. OE Disable Timing (OE Mode Only)
Rev. 1.0
Page 4 of 12
www.sitime.com
SiT2020
-55°C to +125°C, Single-Chip, One-Output Clock Generator
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