SIT5346AECFF628JSA19.123456T datasheet, PDF

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SIT5346AECFF628JSA19.123456T: DescriptionClipped Sine Output Oscillator, 19.123456MHz Nom, QFN-10; CategoryPassive components oscillator; File Size2MB，39 Pages; ManufacturerSiTime; Environmental Compliance

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SIT5346AECFF628JSA19.123456T Overview

Clipped Sine Output Oscillator, 19.123456MHz Nom, QFN-10

SIT5346AECFF628JSA19.123456T Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	SiTime
package instruction	LCC10,.13X.2,58/52/48
Reach Compliance Code	compli
Ageing	0.23 PPM/FIRST YEAR
Frequency Adjustment - Mechanical	NO
frequency stability	0.2%
Installation features	SURFACE MOUNT
Number of terminals	10
Nominal operating frequency	19.123456 MHz
Maximum operating temperature	105 °C
Minimum operating temperature	-40 °C
Oscillator type	CLIPPED SINE
Output impedance	18 Ω
Package body material	CERAMIC
Encapsulate equivalent code	LCC10,.13X.2,58/52/48
physical size	5.15mm x 3.35mm x 1.06mm
Maximum slew rate	53 mA
Maximum supply voltage	3.08 V
Minimum supply voltage	2.52 V
Nominal supply voltage	2.8 V
surface mount	YES

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SiT5346

PRELIMINARY

1 – 60 MHz, ±0.1 to ±0.25 ppm, Endura™ Series Precision Super-TCXO

Description

The

SiT5346

is a ruggedized ±100 ppb precision MEMS

Features



Super-TCXO with a maximum acceleration sensitivity of

0.009 ppb/g or 0.1 ppb/g. Fully compliant to Telcordia GR-

1244-CORE Stratum 3 oscillator specifications, and

engineered for best dynamic performance, the SiT5346 is

ideal for high reliability defense, space, avionics, guidance,

precision GNSS and communications applications.

Leveraging SiTime’s unique DualMEMS™ temperature

sensing and TurboCompensation™ technologies, the

SiT5346 delivers the best dynamic performance for timing

stability in the presence of environmental stressors due to

air flow, temperature perturbation, vibration, shock, and

electromagnetic interference. This device also integrates

multiple on-chip regulators to filter power supply noise,

eliminating the need for a dedicated external LDO.

The SiT5346 offers three device configurations that can be

ordered using

Ordering Codes

for:

1) TCXO with non-pullable output frequency,

2) VCTCXO allowing voltage control of output

frequency, and

3) DCTCXO, enabling digital control of output frequency

using an I

C interface, pullable to 5 ppt (parts per

trillion) resolution.

The SiT5346 can be factory programmed for any

combination of frequency, stability, voltage, and pull range.

Programmability enables designers to optimize clock

configurations while eliminating long lead times and

customization costs associated with quartz devices where

each frequency is custom built.

Refer to

Manufacturing Guideline

for proper reflow profile

and PCB cleaning recommendations for best performance.



Any frequency from 1 MHz to 60 MHz in 1 Hz steps

Factory programmable options for low lead time

Best dynamic stability under airflow, thermal shock



0.009 ppb/g or 0.1 ppb/g acceleration sensitivity



±100 ppb stability across temperature



±1 ppb/C typical frequency slope (ΔF/ΔT)



3e-11 ADEV at 10 second averaging time

-40°C to +105°C operating temperature

No activity dips or micro jumps

Resistant to shock, vibration and board bending

On-chip regulators eliminate the need for external LDOs

Digital frequency pulling (DCTCXO) via I



Digital control of output frequency and pull range



Up to

±3200

ppm pull range



Frequency pull resolution down to 5 ppt

2.5V, 2.8V, 3.0V and 3.3V supply voltage

LVCMOS or clipped sinewave output

RoHS and REACH compliant

Pb-free, Halogen-free, Antimony-free

Contact SiTime

for up-screening and LAT programs

Applications



Ballistics, missiles, munitions

Military portable radios

Ruggedized communications networks

Precision GNSS systems

SATCOM

Transponders

Military, defense, space, avionics systems

Block Diagram

5.0 x 3.2 mm

Package Pinout

SDA / NC

OE / VC / NC

SCL / NC

GND

VDD

CLK

A0 / NC

Figure 1. SiT5346 Block Diagram

Figure 2. Pin Assignments (Top view)

(Refer to

Table 13

for Pin Descriptions)

Rev 0.54

July 22, 2019

www.sitime.com

SiT5346

1 – 60 MHz, ±0.1 to ±0.25 ppm, Endura™ Series Precision Super-TCXO

TABLE OF CONTENTS

PRELIMINARY

Description ................................................................................................................................................................................... 1

Features....................................................................................................................................................................................... 1

Applications ................................................................................................................................................................................. 1

Block Diagram ............................................................................................................................................................................. 1

5.0 x 3.2 mm

Package Pinout ..................................................................................................................................................... 1

Ordering Information .................................................................................................................................................................... 2

Electrical Characteristics.............................................................................................................................................................. 4

Device Configurations and Pin-outs ........................................................................................................................................... 10

Pin-out Top Views............................................................................................................................................................... 10

Test Circuit Diagrams for LVCMOS and Clipped Sinewave Outputs ......................................................................................... 11

Waveforms................................................................................................................................................................................. 13

Timing Diagrams ........................................................................................................................................................................ 14

Typical Performance Plots ......................................................................................................................................................... 15

Architecture Overview ................................................................................................................................................................ 19

Frequency Stability ............................................................................................................................................................. 19

Output Frequency and Format ............................................................................................................................................ 19

Output Frequency Tuning ................................................................................................................................................... 19

Pin 1 Configuration (OE, VC, or NC) .................................................................................................................................. 20

Device Configurations ................................................................................................................................................................ 20

TCXO Configuration ........................................................................................................................................................... 20

VCTCXO Configuration ...................................................................................................................................................... 21

DCTCXO Configuration ...................................................................................................................................................... 22

VCTCXO-Specific Design Considerations ................................................................................................................................. 23

Linearity .............................................................................................................................................................................. 23

Control Voltage Bandwidth ................................................................................................................................................. 23

FV Characteristic Slope K

................................................................................................................................................. 23

Pull Range, Absolute Pull Range ........................................................................................................................................ 24

DCTCXO-Specific Design Considerations ................................................................................................................................. 25

Pull Range and Absolute Pull Range .................................................................................................................................. 25

Output Frequency ............................................................................................................................................................... 26

C Control Registers .......................................................................................................................................................... 28

Register Descriptions.......................................................................................................................................................... 28

Register Address: 0x00. Digital Frequency Control Least Significant Word (LSW) ............................................................ 28

Register Address: 0x01. OE Control, Digital Frequency Control Most Significant Word (MSW) ......................................... 29

[14]

........................................................................................ 30

Serial Interface Configuration Description .......................................................................................................................... 31

Serial Signal Format ........................................................................................................................................................... 31

Parallel Signal Format ........................................................................................................................................................ 32

Parallel Data Format ........................................................................................................................................................... 32

C Timing Specification ...................................................................................................................................................... 34

C Device Address Modes ................................................................................................................................................. 35

Schematic Example ............................................................................................................................................................ 36

Dimensions and Patterns ........................................................................................................................................................... 37

Layout Guidelines ...................................................................................................................................................................... 38

Manufacturing Guidelines .......................................................................................................................................................... 38

Rev 0.54

Page 3 of 39

www.sitime.com

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