A d v a n c e
I n f o r m a t i o n
S71GLxxxNC0
General Description . . . . . . . . . . . . . . . . . . . . . . . . 1
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
MCP Block Diagram (128Mb Flash + 64Mb pSRAM) ..................................5
MCP Block Diagram (256Mb Flash + 64Mb pSRAM) .................................5
MCP Block Diagram (512Mb Flash + 64Mb pSRAM) ..................................6
Table 7. Sector Protection Schemes ......................................58
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 7
512 Mb Flash + 64 Mb pSRAM Pinout .............................................................7
256 Mb Flash + 64 Mb pSRAM Pinout ............................................................8
128 Mb Flash + 64 Mb pSRAM Pinout .............................................................9
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 10
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 11
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 15
TLD084—84-ball Fine-Pitch Ball Grid Array (FBGA) 9.0 x 12.0 x1.2 mm
MCP Compatible Package ................................................................................15
TLA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 8.0 x 11.6 x1.2 mm
MCP Compatible Package ............................................................................... 16
Persistent Protection Mode Lock Bit ........................................................... 58
Password Sector Protection ........................................................................... 59
Password and Password Protection Mode Lock Bit ............................... 59
64-bit Password ..................................................................................................60
Persistent Protection Bit Lock (PPB Lock Bit) ..........................................60
Secured Silicon Sector Flash Memory Region ...........................................60
Write Protect (WP#) ....................................................................................... 62
Hardware Data Protection ............................................................................. 62
Low VCC Write Inhibit ............................................................................... 62
Write Pulse “Glitch” Protection ............................................................... 62
Logical Inhibit ................................................................................................... 62
Power-Up Write Inhibit ............................................................................... 62
Common Flash Memory Interface (CFI) . . . . . . . 62
Table 8. CFI Query Identification String ................................
Table 9. System Interface String..........................................
Table 10. Device Geometry Definition ...................................
Table 11. Primary Vendor-Specific Extended Query ................
63
64
65
66
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 66
Reading Array Data ........................................................................................... 67
Reset Command ................................................................................................. 67
Autoselect Command Sequence ................................................................... 67
Enter Secured Silicon Sector/Exit Secured Silicon
Sector Command Sequence ............................................................................68
Word Program Command Sequence ..........................................................68
Unlock Bypass Command Sequence ........................................................ 69
Write Buffer Programming ......................................................................... 69
Accelerated Program ....................................................................................70
Figure 1. Write Buffer Programming Operation....................... 71
Figure 2. Program Operation ............................................... 72
S29GLxxxN MirrorBit
TM
Flash Family
General Description . . . . . . . . . . . . . . . . . . . . . . . 18
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .20
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
S29GL512N ........................................................................................................23
S29GL256N .......................................................................................................23
S29GL128N .......................................................................................................23
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .24
Table 1. Device Bus Operations ........................................... 24
Program Suspend/Program Resume Command Sequence .................... 72
Figure 3. Program Suspend/Program Resume ........................ 73
VersatileIO
TM
(V
IO
) Control ............................................................................ 24
Requirements for Reading Array Data ........................................................ 24
Page Mode Read ..............................................................................................25
Writing Commands/Command Sequences .................................................25
Write Buffer .....................................................................................................25
Accelerated Program Operation ...............................................................25
Autoselect Functions .................................................................................... 26
Standby Mode ...................................................................................................... 26
Automatic Sleep Mode ..................................................................................... 26
RESET#: Hardware Reset Pin ........................................................................ 26
Output Disable Mode ........................................................................................27
Table 2. Sector Address Table–S29GL512N ........................... 27
Table 3. Sector Address Table–S29GL256N ........................... 42
Table 4. Sector Address Table–S29GL128N ........................... 49
Chip Erase Command Sequence ....................................................................73
Sector Erase Command Sequence ................................................................ 74
Figure 4. Erase Operation ................................................... 75
Erase Suspend/Erase Resume Commands .................................................. 75
Lock Register Command Set Definitions .................................................... 76
Password Protection Command Set Definitions ...................................... 76
Non-Volatile Sector Protection Command Set Definitions .................. 78
Global Volatile Sector Protection Freeze Command Set ...................... 78
Volatile Sector Protection Command Set .................................................. 79
Secured Silicon Sector Entry Command .....................................................80
Secured Silicon Sector Exit Command ........................................................80
Command Definitions ........................................................................................ 81
Table 12. S29GL512N, S29GL256N, S29GL128N Command
Definitions, x16 .................................................................81
Autoselect Mode .................................................................................................53
Table 5. Autoselect Codes, (High Voltage Method) ................ 54
Write Operation Status ...................................................................................84
DQ7: Data# Polling ...........................................................................................84
Figure 5. Data# Polling Algorithm ........................................ 85
Sector Protection ................................................................................................54
Persistent Sector Protection .......................................................................54
Password Sector Protection ........................................................................54
WP# Hardware Protection .........................................................................54
Selecting a Sector Protection Mode .........................................................54
Advanced Sector Protection ...........................................................................55
Lock Register ........................................................................................................55
Table 6. Lock Register ........................................................ 56
RY/BY#: Ready/Busy# ....................................................................................... 85
DQ6: Toggle Bit I ...............................................................................................86
Figure 6. Toggle Bit Algorithm ............................................. 87
DQ2: Toggle Bit II .............................................................................................. 87
Reading Toggle Bits DQ6/DQ2 .....................................................................88
DQ5: Exceeded Timing Limits ........................................................................88
DQ3: Sector Erase Timer ................................................................................88
DQ1: Write-to-Buffer Abort ...........................................................................89
Table 13. Write Operation Status .........................................89
Persistent Sector Protection ...........................................................................56
Dynamic Protection Bit (DYB) ...................................................................56
Persistent Protection Bit (PPB) ..................................................................57
Persistent Protection Bit Lock (PPB Lock Bit) ......................................57
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 90
Figure 7. Maximum Negative Overshoot Waveform................. 90
2
S71GL512_256_128NC0_00_A0 December 17, 2004
A d v a n c e
I n f o r m a t i o n
Figure 8. Maximum Positive
Overshoot Waveform.......................................................... 90
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 90
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 91
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Figure 9. Test Setup ........................................................... 92
Table 14. Test Specifications ............................................... 92
Recommended Operating Conditions . . . . . . . .
Package Capacitance . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . .
107
107
108
109
Key to Switching Waveforms . . . . . . . . . . . . . . . 92
Figure 10. Input Waveforms and Measurement Levels............. 92
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 93
Read-Only Operations–S29GL128N, S29GL256N, S29GL512N ...........93
Figure 11. Read Operation Timings....................................... 94
Figure 12. Page Read Timings.............................................. 94
Read Operation .................................................................................................109
Write Operation ................................................................................................110
Power Down Parameters .................................................................................111
Other Timing Parameters .................................................................................111
AC Test Conditions ..........................................................................................112
AC Measurement Output Load Circuits ....................................................112
Figure 21. AC Output Load Circuit – 16 Mb .......................... 112
Figure 22. AC Output Load Circuit – 32 Mb and 64 Mb .......... 112
Hardware Reset (RESET#) ...............................................................................95
Figure 13. Reset Timings..................................................... 95
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 113
Read Timings ........................................................................................................ 113
Figure 23. Read Timing #1 (Basic Timing)........................... 113
Figure 24. Read Timing #2 (OE# Address Access ................. 113
Figure 25. Read Timing #3 (LB#/UB# Byte Access).............. 114
Figure 26. Read Timing #4 (Page Address Access after CE1# Control
Access for 32M and 64M Only)........................................... 114
Figure 27. Read Timing #5 (Random and Page Address Access for
32M and 64M Only).......................................................... 115
Erase and Program Operations–S29GL128N,
S29GL256N, S29GL512N .................................................................................. 96
Figure 14. Program Operation Timings .................................. 97
Figure 15. Accelerated Program Timing Diagram .................... 97
Figure 16. Chip/Sector Erase Operation Timings..................... 98
Figure 17. Data# Polling Timings
(During Embedded Algorithms) ............................................ 99
Figure 18. Toggle Bit Timings (During Embedded Algorithms) 100
Figure 19. DQ2 vs. DQ6 .................................................... 100
Write Timings .....................................................................................................115
Figure 28. Write Timing #1 (Basic Timing) ..........................
Figure 29. Write Timing #2 (WE# Control) ..........................
Figure 30. Write Timing #3-1(WE#/LB#/UB#
Byte Write Control) ..........................................................
Figure 31. Write Timing #3-3 (WE#/LB#/UB#
Byte Write Control) ..........................................................
Figure 32. Write Timing #3-4 (WE#/LB#/UB#
Byte Write Control) ..........................................................
Figure 33. Read/Write Timing #1-1 (CE1# Control)..............
Figure 34. Read / Write Timing #1-2
(CE1#/WE#/OE# Control) ................................................
Figure 35. Read / Write Timing #2 (OE#, WE# Control)........
Figure 36. Read / Write Timing #3
(OE#, WE#, LB#, UB# Control).........................................
Figure 37. Power-up Timing #1 .........................................
Figure 38. Power-up Timing #2 .........................................
Figure 39. Power Down Entry and Exit Timing......................
Figure 40. Standby Entry Timing after Read or Write ............
Figure 41. Power Down Program Timing (for 32M/64M Only) .
115
116
116
117
117
118
118
119
119
120
120
120
121
121
Alternate CE# Controlled Erase and Program Operations-
S29GL128N, S29GL256N, S29GL512N .........................................................101
Figure 20. Alternate CE# Controlled Write (Erase/
Program) Operation Timings.............................................. 102
Erase And Programming Performance . . . . . . 103
TSOP Pin and BGA Package Capacitance . . . . 103
Read/Write Timings ..........................................................................................118
pSRAM Type 7
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . .
Power Down (for 32M, 64M Only) . . . . . . . . . . .
104
104
105
105
Power Down ...................................................................................................... 105
Power Down Program Sequence .................................................................106
Address Key .......................................................................................................106
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 107
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 122
December 17, 2004 S71GL512_256_128NC0_00_A0
3
stm32/stm8
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