STD4N62K3
STU4N62K3
N-channel 620 V, 1.8
Ω,
3.8 A SuperMESH3™ Power MOSFET
DPAK, IPAK
Preliminary data
Features
Type
STD4N62K3
STU4N62K3
■
■
■
■
■
■
V
DSS
620 V
R
DS(on)
max
< 1.95
Ω
I
D
3.8 A
Pw
70 W
3
1
2
1
3
100% avalanche tested
Extremely high dv/dt capability
Gate charge minimized
Very low intrinsic capacitances
Improved diode reverse recovery
characteristics
Zener-protected
DPAK
IPAK
Figure 1.
Internal schematic diagram
D(2)
Application
■
Switching applications
Description
These devices are made using the
SuperMESH3™ Power MOSFET technology that
is obtained via improvements applied to
STMicroelectronics’ SuperMESH™ technology
combined with a new optimized vertical structure.
The resulting product has an extremely low on
resistance, superior dynamic performance and
high avalanche capability, making it especially
suitable for the most demanding applications.
Table 1.
Device summary
Marking
4N62K3
G(1)
S(3)
AM01476v1
Order codes
STD4N62K3
STU4N62K3
Package
DPAK
IPAK
Packaging
Tape and reel
Tube
May 2010
Doc ID 17549 Rev 1
1/12
www.st.com
12
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
Contents
STD4N62K3, STU4N62K3
Contents
1
2
3
4
5
6
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Test circuits
.............................................. 6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2/12
Doc ID 17549 Rev 1
STD4N62K3, STU4N62K3
Electrical ratings
1
Electrical ratings
Table 2.
Symbol
V
DS
V
GS
I
D
I
D
I
DM (1)
P
TOT
I
AR
E
AS
V
ESD(G-S)
dv/dt
(2)
T
stg
T
j
Absolute maximum ratings
Parameter
Drain-source voltage (V
GS
= 0)
Gate- source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Avalanche current, repetitive or not-
repetitive (pulse width limited by T
j
max)
Single pulse avalanche energy
(starting T
j
= 25°C, I
D
= I
AR
, V
DD
= 50V)
Gate source ESD(HBM-C = 100 pF,
R = 1.5 kΩ)
Peak diode recovery voltage slope
Storage temperature
Max. operating junction temperature
Value
620
± 30
3.8
2
15.2
70
3.8
TBD
2500
12
- 55 to 150
150
Unit
V
V
A
A
A
W
A
mJ
V
V/ns
°C
°C
1. Pulse width limited by safe operating area
2. I
SD
≤
3.8 A, di/dt = 200 A/µs, V
DD
= 80% V
(BR)DSS.
Table 3.
Symbol
Thermal data
Value
Parameter
DPAK
IPAK
1.79
50
100
300
°C/W
°C/W
°C/W
°C
Unit
R
thj-case
Thermal resistance junction-case max
R
thj-pcb(1)
Thermal resistance junction-pcb max
R
thj-amb
T
l
Thermal resistance junction-ambient max
Maximum lead temperature for soldering
purpose
1. When mounted on 1inch² FR-4 board, 2 oz Cu
Doc ID 17549 Rev 1
3/12
Electrical characteristics
STD4N62K3, STU4N62K3
2
Electrical characteristics
(T
C
= 25 °C unless otherwise specified)
Table 4.
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on
On /off states
Parameter
Drain-source
breakdown voltage
Test conditions
I
D
= 1 mA, V
GS
= 0
Min.
620
1
50
± 10
3
3.75
1.8
4.5
1.95
Typ.
Max.
Unit
V
µA
µA
µA
V
Ω
V
DS
= Max rating
Zero gate voltage
drain current (V
GS
= 0) V
DS
= Max rating, T
C
=125 °C
Gate-body leakage
current (V
DS
= 0)
V
GS
= ± 20 V
Gate threshold voltage V
DS
= V
GS
, I
D
= 50 µA
Static drain-source on
resistance
V
GS
= 10 V, I
D
= 1.9 A
Table 5.
Symbol
C
iss
C
oss
C
rss
(1)
Dynamic
Parameter
Input capacitance
Output capacitance
Reverse transfer
capacitance
Equivalent
capacitance time
related
Equivalent
capacitance energy
related
Intrinsic gate
resistance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
= 0 to 496 V, V
GS
= 0
-
TBD
-
pF
Test conditions
Min.
Typ.
450
60
10
Max.
Unit
pF
pF
pF
V
DS
= 50 V, f = 1 MHz,
V
GS
= 0
-
-
C
o(tr)
-
TBD
-
pF
C
o(er)(2)
R
G
Q
g
Q
gs
Q
gd
f = 1 MHz open drain
V
DD
= 496 V, I
D
= 3.8 A,
V
GS
= 10 V
(see
Figure 3)
-
TBD
14
TBD
TBD
-
Ω
nC
nC
nC
-
-
1. Time related is defined as a constant equivalent capacitance giving the same charging time as C
oss
when
V
DS
increases from 0 to 80% V
DSS
2. Energy related is defined as a constant equivalent capacitance giving the same stored energy as C
oss
when V
DS
increases from 0 to 80% V
DSS
4/12
Doc ID 17549 Rev 1
STD4N62K3, STU4N62K3
Electrical characteristics
Table 6.
Symbol
t
d(on)
t
r
t
d(off)
t
f
Switching times
Parameter
Turn-on delay time
Rise time
Turn-off-delay time
Fall time
Test conditions
V
DD
= 300 V, I
D
= 1.9 A,
R
G
= 4.7
Ω,
V
GS
= 10 V
(see
Figure 2)
Min.
Typ.
TBD
TBD
TBD
TBD
Max
Unit
ns
ns
ns
ns
-
-
Table 7.
Symbol
I
SD
I
SDM
(1)
Source drain diode
Parameter
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
SD
= 3.8 A, V
GS
= 0
I
SD
= 3.8 A, di/dt = 100 A/µs
V
DD
= 60 V (see
Figure 7)
I
SD
= 3.8 A, di/dt = 100 A/µs
V
DD
= 60 V, T
j
= 150 °C
(see
Figure 7)
Test conditions
Min.
-
-
-
TBD
TBD
TBD
TBD
TBD
TBD
Typ.
Max. Unit
3.8
15.2
1.6
A
A
V
ns
nC
A
ns
nC
A
V
SD (2)
t
rr
Q
rr
I
RRM
t
rr
Q
rr
I
RRM
-
1. Pulse width limited by safe operating area
2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%
Table 8.
Symbol
BV
GSO(1)
Gate-source Zener diode
Parameter
Gate-source breakdown
voltage
Test conditions
Igs=± 1 mA (open drain)
Min.
30
Typ.
-
Max. Unit
V
1. The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components
Doc ID 17549 Rev 1
5/12
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