A40MX04-PQ100B datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Programmable logic devices> Programmable logic> A40MX04-PQ100B

A40MX04-PQ100B: DescriptionFPGA, 295 CLBS, 2000 GATES, 48.24 MHz, PQFP100; CategoryProgrammable logic devices Programmable logic; File Size7MB，142 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

Download Datasheet Parametric View All

A40MX04-PQ100B Overview

FPGA, 295 CLBS, 2000 GATES, 48.24 MHz, PQFP100

A40MX04-PQ100B Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Microsemi
package instruction	QFP,
Reach Compliance Code	compli
ECCN code	3A001.A.2.C
Other features	CAN ALSO BE OPERATED AT 5.0V
maximum clock frequency	80.4 MHz
Combined latency of CLB-Max	2.66 ns
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
length	20 mm
Humidity sensitivity level	3
Configurable number of logic blocks	547
Equivalent number of gates	4000
Number of terminals	100
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	547 CLBS, 4000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Package shape	RECTANGULAR
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	225
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	3.4 mm
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	14 mm

Preview

Download Datasheet

View All

Revision 11

40MX and 42MX FPGA Families

Features

High Capacity

•

Single-Chip ASIC Alternative

3,000 to 54,000 System Gates

Up to 2.5 kbits Configurable Dual-Port SRAM

Fast Wide-Decode Circuitry

Up to 202 User-Programmable I/O Pins

5.6 ns Clock-to-Out

250 MHz Performance

5 ns Dual-Port SRAM Access

100 MHz FIFOs

7.5 ns 35-Bit Address Decode

•

HiRel Features

•

Commercial, Industrial, Automotive,

Temperature Plastic Packages

and

Military

Commercial, Military Temperature, and MIL-STD-883

Ceramic Packages

QML Certification

Ceramic Devices Available to DSCC SMD

Mixed-Voltage Operation (5.0V or 3.3V for core and

I/Os), with PCI-Compliant I/Os

Up to 100% Resource Utilization and 100% Pin Locking

Deterministic, User-Controllable Timing

Unique In-System Diagnostic and Verification Capability

with Silicon Explorer II

Low Power Consumption

IEEE Standard 1149.1 (JTAG) Boundary Scan Testing

Ease of Integration

High Performance

Product Profile

Device

Capacity

System Gates

SRAM Bits

Logic Modules

Sequential

Combinatorial

Decode

Clock-to-Out

SRAM Modules

(64x4 or 32x8)

Dedicated Flip-Flops

Maximum Flip-Flops

Clocks

User I/O (maximum)

PCI

Boundary Scan Test (BST)

Packages (by pin count)

PLCC

PQFP

VQFP

TQFP

CQFP

PBGA

A40MX02

3,000

–

295

–

9.5 ns

–

147

–

44, 68

100

–

A40MX04

6,000

–

547

–

9.5 ns

–

273

–

44, 68, 84

100

–

A42MX09

14,000

–

348

336

–

5.6 ns

–

348

516

104

–

100, 160

100

176

–

A42MX16

24,000

–

624

608

–

6.1 ns

–

624

928

140

–

100, 160, 208

100

176

–

A42MX24

36,000

–

954

912

6.1 ns

–

954

1,410

176

Yes

160, 208

–

176

–

A42MX36

54,000

2,560

1,230

1,184

6.3 ns

1,230

1,822

202

Yes

–

208, 240

–

208, 256

272

May 2012

40MX and 42MX FPGA Families

Table of Contents

40MX and 42MX FPGA Families

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

MX Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

Development Tool Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

5.0 V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

3.3 V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19

Mixed 5.0 V / 3.3 V Operating Conditions (for 42MX Devices Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21

Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27

Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-35

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-83

Package Pin Assignments

PL44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

PL68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

PL84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

PQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

PQ160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

PQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

PQ240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26

VQ80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30

VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32

TQ176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34

CQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40

CQ256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43

BG272 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

R ev i si o n 1 1

1 – 40MX and 42MX FPGA Families

General Description

Microsemi's 40MX and 42MX families offer a cost-effective design solution at 5V. The MX devices are

single-chip solutions and provide high performance while shortening the system design and development

cycle. MX devices can integrate and consolidate logic implemented in multiple PALs, CPLDs, and

FPGAs. Example applications include high-speed controllers and address decoding, peripheral bus

interfaces, DSP, and co-processor functions.

The MX device architecture is based on Microsemi’s patented antifuse technology implemented in a

0.45µm triple-metal CMOS process. With capacities ranging from 3,000 to 54,000 system gates, the MX

devices provide performance up to 250 MHz, are live on power-up and have one-fifth the standby power

consumption of comparable FPGAs. MX FPGAs provide up to 202 user I/Os and are available in a wide

variety of packages and speed grades.

A42MX24 and A42MX36 devices also feature MultiPlex I/Os, which support mixed-voltage systems,

enable programmable PCI, deliver high-performance operation at both 5.0V and 3.3V, and provide a low-

power mode. The devices are fully compliant with the PCI Local Bus Specification (version 2.1). They

deliver 200 MHz on-chip operation and 6.1 ns clock-to-output performance.

The 42MX24 and 42MX36 devices include system-level features such as IEEE Standard 1149.1 (JTAG)

Boundary Scan Testing and fast wide-decode modules. In addition, the A42MX36 device offers dual-port

SRAM for implementing fast FIFOs, LIFOs, and temporary data storage. The storage elements can

efficiently address applications requiring wide datapath manipulation and can perform transformation

functions such as those required for telecommunications, networking, and DSP.

All MX devices are fully tested over automotive and military temperature ranges. In addition, the largest

member of the family, the A42MX36, is available in both CQ208 and CQ256 ceramic packages screened

to MIL-STD-883 levels. For easy prototyping and conversion from plastic to ceramic, the CQ208 and

PQ208 devices are pin-compatible.

MX Architectural Overview

The MX devices are composed of fine-grained building blocks that enable fast, efficient logic designs. All

devices within these families are composed of logic modules, I/O modules, routing resources and clock

networks, which are the building blocks for fast logic designs. In addition, the A42MX36 device contains

embedded dual-port SRAM modules, which are optimized for high-speed datapath functions such as

FIFOs, LIFOs and scratchpad memory. A42MX24 and A42MX36 also contain wide-decode modules.

Logic Modules

The 40MX logic module is an eight-input, one-output logic circuit designed to implement a wide range of

logic functions with efficient use of interconnect routing resources (Figure

1-1 on page 1-2).

The logic module can implement the four basic logic functions (NAND, AND, OR and NOR) in gates of

two, three, or four inputs. The logic module can also implement a variety of D-latches, exclusivity

functions, AND-ORs and OR-ANDs. No dedicated hard-wired latches or flip-flops are required in the

array; latches and flip-flops can be constructed from logic modules whenever required in the

application.

R ev i si o n 1 1

1 -1

Recommended Resources

Stator coil connection method a

Basic application circuit of five-terminal adjustable integrated voltage regulator

push button telephone dialing circuit

ISFET measurement circuit

Sensor temperature compensation principle circuit

Power frequency 0-5 minute delay circuit diagram

Help, 80c51: Use Proteus to build an 8-way answering system based on 80c51. The first person to press the button will have the corresponding light on, and others will not light up when they press it....; z2661213 Embedded System

How can this damped oscillation waveform be generated?: Hi everyone, the waveform in the above figure is a damped oscillation waveform generated by charging an inductor for 5us and discharging it. How can I realize this circuit? Thank you....; PSIR RF/Wirelessly

[EEWORLD module arrangement] + ultrasonic module: [i=s] This post was last edited by paulhyde on 2014-9-15 03:01 [/i] [local]1[/loc for your convenience...; kevinswen Electronics Design Contest

Ov7670 image acquisition source program based on TINYM0 LPC1114: [size=4]After a month of preparation and two weeks of program debugging, the application of TINYM0 development board (LPC1114 chip) was realized. The image was collected by OV7670 with FIFO image acqu...; 灞波儿奔 Microcontroller MCU

Pingtouge Scenario-based Bluetooth Mesh Gateway Program Burning: To burn the Pingtou Ge scenario-based Bluetooth Mesh gateway program, you need to refer to thedocument and use thesoftware package andtool. If you only read the manual, there are still some places tha...; littleshrimp Domestic Chip Exchange

Introduction to allegro file encryption method: [p=26, null, left][color=rgb(0, 0, 0)][size=3]Sometimes you need to send a PCB drawing to someone else, but you don’t want them to operate on the file. There are two ways to do this: one is to prevent...; ohahaha PCB Design

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components