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A40MX04-VQG100A

Description
FPGA, 295 CLBS, 2000 GATES, 48.24 MHz, PQFP100
Categorysemiconductor    Programmable logic devices   
File Size7MB,142 Pages
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
Download Datasheet Parametric View All

A40MX04-VQG100A Overview

FPGA, 295 CLBS, 2000 GATES, 48.24 MHz, PQFP100

A40MX04-VQG100A Parametric

Parameter NameAttribute value
Number of terminals100
Minimum operating temperature-55 Cel
Maximum operating temperature125 Cel
Processing package descriptionPLASTIC, MO-108, QFP-100
each_compliYes
stateActive
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
clock_frequency_max48.24 MHz
The maximum delay of a CLB module3.72 ns
jesd_30_codeR-PQFP-G100
jesd_609_codee0
moisture_sensitivity_level3
Number of configurable logic modules295
Number of equivalent gate circuits2000
organize295 CLBS, 2000 GATES
Packaging MaterialsPLASTIC/EPOXY
ckage_codeQFP
packaging shapeRECTANGULAR
Package SizeFLATPACK
eak_reflow_temperature__cel_225
qualification_statusCOMMERCIAL
seated_height_max3.4 mm
Rated supply voltage3.3 V
surface mountYES
CraftsmanshipCMOS
Temperature levelMILITARY
terminal coatingTIN LEAD
Terminal formGULL WING
Terminal spacing0.6500 mm
Terminal locationQUAD
ime_peak_reflow_temperature_max__s_30
length20 mm
width14 mm
dditional_featureCAN ALSO BE OPERATED AT 5.0V
Revision 11
40MX and 42MX FPGA Families
Features
High Capacity
Single-Chip ASIC Alternative
3,000 to 54,000 System Gates
Up to 2.5 kbits Configurable Dual-Port SRAM
Fast Wide-Decode Circuitry
Up to 202 User-Programmable I/O Pins
5.6 ns Clock-to-Out
250 MHz Performance
5 ns Dual-Port SRAM Access
100 MHz FIFOs
7.5 ns 35-Bit Address Decode
HiRel Features
Commercial, Industrial, Automotive,
Temperature Plastic Packages
and
Military
Commercial, Military Temperature, and MIL-STD-883
Ceramic Packages
QML Certification
Ceramic Devices Available to DSCC SMD
Mixed-Voltage Operation (5.0V or 3.3V for core and
I/Os), with PCI-Compliant I/Os
Up to 100% Resource Utilization and 100% Pin Locking
Deterministic, User-Controllable Timing
Unique In-System Diagnostic and Verification Capability
with Silicon Explorer II
Low Power Consumption
IEEE Standard 1149.1 (JTAG) Boundary Scan Testing
Ease of Integration
High Performance
Product Profile
Device
Capacity
System Gates
SRAM Bits
Logic Modules
Sequential
Combinatorial
Decode
Clock-to-Out
SRAM Modules
(64x4 or 32x8)
Dedicated Flip-Flops
Maximum Flip-Flops
Clocks
User I/O (maximum)
PCI
Boundary Scan Test (BST)
Packages (by pin count)
PLCC
PQFP
VQFP
TQFP
CQFP
PBGA
A40MX02
3,000
295
9.5 ns
147
1
57
44, 68
100
80
A40MX04
6,000
547
9.5 ns
273
1
69
44, 68, 84
100
80
A42MX09
14,000
348
336
5.6 ns
348
516
2
104
84
100, 160
100
176
A42MX16
24,000
624
608
6.1 ns
624
928
2
140
84
100, 160, 208
100
176
A42MX24
36,000
954
912
24
6.1 ns
954
1,410
2
176
Yes
Yes
84
160, 208
176
A42MX36
54,000
2,560
1,230
1,184
24
6.3 ns
10
1,230
1,822
6
202
Yes
Yes
208, 240
208, 256
272
May 2012
© 2012 Microsemi Corporation
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