A42MX24-2PL208M datasheet, PDF

Datasheet> All Categories > semiconductor> Programmable logic devices> A42MX24-2PL208M

A42MX24-2PL208M: DescriptionFPGA, 295 CLBS, 2000 GATES, 48.24 MHz, PQFP100; Categorysemiconductor Programmable logic devices; File Size7MB，142 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

Download Datasheet Parametric View All

A42MX24-2PL208M Overview

FPGA, 295 CLBS, 2000 GATES, 48.24 MHz, PQFP100

A42MX24-2PL208M Parametric

Parameter Name	Attribute value
Number of terminals	100
Minimum operating temperature	-55 Cel
Maximum operating temperature	125 Cel
Processing package description	PLASTIC, MO-108, QFP-100
each_compli	Yes
state	Active
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
clock_frequency_max	48.24 MHz
The maximum delay of a CLB module	3.72 ns
jesd_30_code	R-PQFP-G100
jesd_609_code	e0
moisture_sensitivity_level	3
Number of configurable logic modules	295
Number of equivalent gate circuits	2000
organize	295 CLBS, 2000 GATES
Packaging Materials	PLASTIC/EPOXY
ckage_code	QFP
packaging shape	RECTANGULAR
Package Size	FLATPACK
eak_reflow_temperature__cel_	225
qualification_status	COMMERCIAL
seated_height_max	3.4 mm
Rated supply voltage	3.3 V
surface mount	YES
Craftsmanship	CMOS
Temperature level	MILITARY
terminal coating	TIN LEAD
Terminal form	GULL WING
Terminal spacing	0.6500 mm
Terminal location	QUAD
ime_peak_reflow_temperature_max__s_	30
length	20 mm
width	14 mm
dditional_feature	CAN ALSO BE OPERATED AT 5.0V

Preview

Download Datasheet

View All

Revision 11

40MX and 42MX FPGA Families

Features

High Capacity

•

Single-Chip ASIC Alternative

3,000 to 54,000 System Gates

Up to 2.5 kbits Configurable Dual-Port SRAM

Fast Wide-Decode Circuitry

Up to 202 User-Programmable I/O Pins

5.6 ns Clock-to-Out

250 MHz Performance

5 ns Dual-Port SRAM Access

100 MHz FIFOs

7.5 ns 35-Bit Address Decode

•

HiRel Features

•

Commercial, Industrial, Automotive,

Temperature Plastic Packages

and

Military

Commercial, Military Temperature, and MIL-STD-883

Ceramic Packages

QML Certification

Ceramic Devices Available to DSCC SMD

Mixed-Voltage Operation (5.0V or 3.3V for core and

I/Os), with PCI-Compliant I/Os

Up to 100% Resource Utilization and 100% Pin Locking

Deterministic, User-Controllable Timing

Unique In-System Diagnostic and Verification Capability

with Silicon Explorer II

Low Power Consumption

IEEE Standard 1149.1 (JTAG) Boundary Scan Testing

Ease of Integration

High Performance

Product Profile

Device

Capacity

System Gates

SRAM Bits

Logic Modules

Sequential

Combinatorial

Decode

Clock-to-Out

SRAM Modules

(64x4 or 32x8)

Dedicated Flip-Flops

Maximum Flip-Flops

Clocks

User I/O (maximum)

PCI

Boundary Scan Test (BST)

Packages (by pin count)

PLCC

PQFP

VQFP

TQFP

CQFP

PBGA

A40MX02

3,000

–

295

–

9.5 ns

–

147

–

44, 68

100

–

A40MX04

6,000

–

547

–

9.5 ns

–

273

–

44, 68, 84

100

–

A42MX09

14,000

–

348

336

–

5.6 ns

–

348

516

104

–

100, 160

100

176

–

A42MX16

24,000

–

624

608

–

6.1 ns

–

624

928

140

–

100, 160, 208

100

176

–

A42MX24

36,000

–

954

912

6.1 ns

–

954

1,410

176

Yes

160, 208

–

176

–

A42MX36

54,000

2,560

1,230

1,184

6.3 ns

1,230

1,822

202

Yes

–

208, 240

–

208, 256

272

May 2012

40MX and 42MX FPGA Families

Table of Contents

40MX and 42MX FPGA Families

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

MX Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

Development Tool Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

5.0 V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

3.3 V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19

Mixed 5.0 V / 3.3 V Operating Conditions (for 42MX Devices Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21

Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27

Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-35

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-83

Package Pin Assignments

PL44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

PL68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

PL84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

PQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

PQ160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

PQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

PQ240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26

VQ80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30

VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32

TQ176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34

CQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40

CQ256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43

BG272 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

R ev i si o n 1 1

1 – 40MX and 42MX FPGA Families

General Description

Microsemi's 40MX and 42MX families offer a cost-effective design solution at 5V. The MX devices are

single-chip solutions and provide high performance while shortening the system design and development

cycle. MX devices can integrate and consolidate logic implemented in multiple PALs, CPLDs, and

FPGAs. Example applications include high-speed controllers and address decoding, peripheral bus

interfaces, DSP, and co-processor functions.

The MX device architecture is based on Microsemi’s patented antifuse technology implemented in a

0.45µm triple-metal CMOS process. With capacities ranging from 3,000 to 54,000 system gates, the MX

devices provide performance up to 250 MHz, are live on power-up and have one-fifth the standby power

consumption of comparable FPGAs. MX FPGAs provide up to 202 user I/Os and are available in a wide

variety of packages and speed grades.

A42MX24 and A42MX36 devices also feature MultiPlex I/Os, which support mixed-voltage systems,

enable programmable PCI, deliver high-performance operation at both 5.0V and 3.3V, and provide a low-

power mode. The devices are fully compliant with the PCI Local Bus Specification (version 2.1). They

deliver 200 MHz on-chip operation and 6.1 ns clock-to-output performance.

The 42MX24 and 42MX36 devices include system-level features such as IEEE Standard 1149.1 (JTAG)

Boundary Scan Testing and fast wide-decode modules. In addition, the A42MX36 device offers dual-port

SRAM for implementing fast FIFOs, LIFOs, and temporary data storage. The storage elements can

efficiently address applications requiring wide datapath manipulation and can perform transformation

functions such as those required for telecommunications, networking, and DSP.

All MX devices are fully tested over automotive and military temperature ranges. In addition, the largest

member of the family, the A42MX36, is available in both CQ208 and CQ256 ceramic packages screened

to MIL-STD-883 levels. For easy prototyping and conversion from plastic to ceramic, the CQ208 and

PQ208 devices are pin-compatible.

MX Architectural Overview

The MX devices are composed of fine-grained building blocks that enable fast, efficient logic designs. All

devices within these families are composed of logic modules, I/O modules, routing resources and clock

networks, which are the building blocks for fast logic designs. In addition, the A42MX36 device contains

embedded dual-port SRAM modules, which are optimized for high-speed datapath functions such as

FIFOs, LIFOs and scratchpad memory. A42MX24 and A42MX36 also contain wide-decode modules.

Logic Modules

The 40MX logic module is an eight-input, one-output logic circuit designed to implement a wide range of

logic functions with efficient use of interconnect routing resources (Figure

1-1 on page 1-2).

The logic module can implement the four basic logic functions (NAND, AND, OR and NOR) in gates of

two, three, or four inputs. The logic module can also implement a variety of D-latches, exclusivity

functions, AND-ORs and OR-ANDs. No dedicated hard-wired latches or flip-flops are required in the

array; latches and flip-flops can be constructed from logic modules whenever required in the

application.

R ev i si o n 1 1

1 -1

Recommended Resources

Voltage adjustable circuit diagram

Simple refrigerator protector circuit

Language filter circuit

555 "Lost Box" circuit for training rats

PC CPU overheating language warning circuit

820e computer motherboard circuit diagram_49

What do I need to learn about embedded systems?: Embedded is one of the most popular and promising IT application fields. Mobile phones, PDAs, electronic dictionaries, videophones, VCD/DVD/MP3 players, digital cameras (DC), digital video cameras (DV...; djdhn Embedded System

Getting Started with Microcontrollers: Tutorials for learning MCUs are already very common. Let me briefly introduce them! I have been in contact with MCUs for 6 months and I find them very interesting. MCUs are just like that. As long as ...; wydz123 DIY/Open Source Hardware

Using ARM to implement serial and parallel issues of ADC data acquisition: The whole system has two 18-bit ADC sampling outputs, one of which (a) has a sampling frequency of 162k, and the other (b) has a sampling frequency of 324k, which is twice as high. The relationship be...; lovelywuwu ARM Technology

AT89C51 serial communication problem!: Teachers, I am a novice! I copied the hexadecimal data FF 00 07 8E FF sent by a serial port on the Internet. But when I simulated, the serial port saw FF FF 00 00 07 07 8E 8E FF FF. Why? Please give m...; gjinzi Embedded System

The Rubik's Cube that embodies the charm of electronic engineering: [i=s]This post was last edited by ljj3166 on 2015-1-12 14:06[/i] [size=3]Some time ago, there was a Rubik's Cube prize in an ADI event[/size] [size=3]Although the author did not win the prize, when I ...; ljj3166 Robotics Development

Audio codec ground processing: Recently, when debugging an audio codec, a noise interference problem occurred. When there is no signal input, when the volume is increased to the maximum, a needle squeaking sound can be clearly hear...; audioapp PCB Design

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components