TSPC860SRMZPU66B datasheet, PDF

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TSPC860SRMZPU66B: DescriptionRISC Microprocessor, 32-Bit, 66MHz, CMOS, PBGA357, PLASTIC, BGA-357; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，90 Pages; ManufacturerAtmel (Microchip)

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TSPC860SRMZPU66B Overview

RISC Microprocessor, 32-Bit, 66MHz, CMOS, PBGA357, PLASTIC, BGA-357

TSPC860SRMZPU66B Parametric

Parameter Name	Attribute value
Maker	Atmel (Microchip)
Parts packaging code	BGA
package instruction	BGA,
Contacts	357
Reach Compliance Code	unknow
ECCN code	3A001.A.2.C
Address bus width	32
bit size	32
boundary scan	YES
maximum clock frequency	66 MHz
External data bus width	32
Format	FIXED POINT
Integrated cache	YES
JESD-30 code	S-PBGA-B357
length	25 mm
low power mode	YES
Number of terminals	357
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Certification status	Not Qualified
Maximum seat height	2.05 mm
speed	66 MHz
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	25 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC

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Features

•

PowerPC

Single Issue Integer Core

•

Precise Exception Model

•

Extensive System Development Support

– On-chip Watchpoints and Breakpoints

– Program Flow Tracking

– On-chip Emulation (Once) Development Interface

High Performance (Dhrystone 2.1: 52 MIPS at 50 MHz, 3.3V, 1.3 Watts Total Power)

Low Power (< 241 mW at 25 MHz, 2.4V Internal, 3.3V I/O-core, Caches, MMUs, I/O)

MPC8XX PowerPC System Interface, Including a Periodic Interrupt Timer, a Bus

Monitor, and Real-time Clocks

Single Issue, 32-bit Version of the Embedded PowerPC Core (Fully Compatible with

Book 1 of the PowerPC Architecture Definition) with 32 x 32-bit Fixed Point Registers

– Embedded PowerPC Performs Branch Folding, Branch Prediction with

Conditional Prefetch, without Conditional Execution

– 4-Kbyte Data Cache and 4-Kbyte Instruction Cache, Each with an MMU

– Instruction and Data Caches are Two-way, Set Associative, Physical Address,

4 Word Line Burst, Least Recently Used (LRU) Replacement, Lockable On-line

Granularity

– MMUs with 32 Entry TLB, Fully Associative Instruction and Data TLBs

– MMUs Support Multiple Page Sizes of 4 KB, 16 KB, 256 KB, 512 KB and 8 MB;

16 Virtual Address Spaces and 8 Protection Groups

– Advanced On-chip Emulation Debug Mode

Up to 32-bit Data Bus (Dynamic Bus Sizing for 8- and 16-bit)

32 Address Lines

Fully Static Design

= +3.3V ± 5%

max

= 66 MHz (80 MHz (TBC))

Military Temperature Range: -55°C < T

< +125°C

= 0.75 W Typical at 66 MHz

•

32-bit Quad

Integrated

Power QUICC™

Communication

Controller

TSPC860

•

Description

The TSPC860 PowerPC QUad Integrated Communication Controller (Power

QUICC

™

) is a versatile one-chip integrated microprocessor and peripheral combina-

tion that can be used in a variety of controller applications. It particularly excels in

communications and networking systems. The Power QUICC (pronounced “quick”)

can be described as a PowerPC-based derivative of the TS68EN360 (QUICC

™

The CPU on the TSPC860 is a 32-bit PowerPC implementation that incorporates

memory management units (MMUs) and instruction and data caches. The communi-

cations processor module (CPM) of the TS68EN360 QUICC has been enhanced with

the addition of a Two-wire Interface (TWI) compatible with protocols such as I

C. Mod-

erate to high digital signal processing (DSP) functionality has been added to the CPM.

The memory controller has been enhanced, enabling the TSPC860 to support any

type of memory, including high performance memories and newer dynamic random

access memories (DRAMs). Overall system functionality is completed with the addi-

tion of a PCMCIA socket controller supporting up to two sockets and a real-time clock.

PBGA 357

ZP suffix

Rev. 2129A–HIREL–08/02

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