ACST4
Overvoltage protected AC switch
Features
■
■
■
■
Triac with overvoltage protection
Low I
GT
(<10 mA) or high immunity
(I
GT
<35 mA) version
High noise immunity: static dV/dt > 1000 V/µs
TO-220FPAB insulated package: 1500 V rms
OUT
G
COM
G
OUT
COM
Benefits
■
■
■
■
■
Enables equipment to meet IEC 61000-4-5
High off-state reliability with planar technology
Needs no external overvoltage protection
Reduces the power passive component count
High immunity against fast transients
described in IEC 61000-4-4 standards
DPAK
ACST410-8B
ACST435-8B
TO-220FPAB
ACST410-8FP
ACST435-8FP
Figure 1.
Functional diagram
OUT
Applications
■
■
AC mains static switching in appliance and
industrial control systems
Drive of medium power AC loads such as:
– Universal motor of washing machine drum
– Compressor for fridge or air conditioner
Table 1.
Symbol
I
T(RMS)
V
DRM
/V
RRM
G
COM
Device summary
Value
4
800
10
35
Unit
A
V
mA
mA
Description
The ACST4 series belongs to the ACS™/ACST
power switch family built with A.S.D.
®
(application
specific discrete) technology. This high
performance device is suited to home appliances
or industrial systems, and drives loads up to 4 A.
This ACST4 switch embeds a Triac structure and
a high voltage clamping device able to absorb the
inductive turn-off energy and withstand line
transients such as those described in the
IEC 61000-4-5 standards. The ACST410 needs
only a low gate current to be activated (I
GT
< 10
mA) and still shows a high noise immunity
complying with IEC standards such as
IEC 61000-4-4 (fast transient burst test).
I
GT
(ACST410)
I
GT
(ACST435)
TM: ACS is a trademark of STMicroelectronics.
®: A.S.D. is a registered trademark of
STMicroelectronics
December 2009
Doc ID 8766 Rev 5
1/13
www.st.com
13
Characteristics
ASCT4
1
Table 2.
Symbol
Characteristics
Absolute ratings (limiting values)
Parameter
TO-220FPAB
I
T(RMS)
On-state rms current (full sine wave)
DPAK
T
c
= 102 °C
T
c
= 112 °C
1
32
30
6
100
2
0.1
10
1.6
-40 to +150
-40 to +125
260
1500
A
A
A
2
s
A/µs
kV
W
W
A
°C
°C
°C
V
Value
4
A
Unit
DPAK with
T
amb
= 60 °C
0.5 cm
2
copper
I
TSM
I
2
t
dI/dt
V
PP
P
G(AV)
P
GM
I
GM
T
stg
T
j
T
l
Non repetitive surge peak on-state current F = 60 Hz
T
j
initial = 25 °C, ( full cycle sine wave)
F = 50 Hz
I
2
t for fuse selection
Critical rate of rise on-state current
I
G
= 2 x I
GT,
(t
r
≤
100 ns)
Non repetitive line peak pulse voltage
(1)
Average gate power dissipation
Peak gate power dissipation (t
p
= 20 µs)
Peak gate current (t
p
= 20 µs)
Storage temperature range
Operating junction temperature range
Maximum lead solder temperature during 10 ms (at 3 mm from plastic case)
TO-220FPAB
F = 120 Hz
t
p
= 16.7 ms
t
p
= 20 ms
t
p
= 10 ms
T
j
= 125 °C
T
j
= 25 °C
T
j
= 125 °C
T
j
= 125 °C
T
j
= 125 °C
V
INS(RMS)
Insulation rms voltage
1. According to test described in IEC 61000-4-5 standard and
Figure 19.
Table 3.
Symbol
I
GT(1)
V
GT
V
GD
I
H(2)
I
L
Electrical characteristics
Test conditions
V
OUT
= 12 V, R
L
= 33
Ω
V
OUT
= 12 V, R
L
= 33
Ω
V
OUT
= V
DRM,
R
L
= 3.3 kΩ
I
OUT
= 500 mA
I
G
= 1.2 x I
GT
I - II - III
Quadrant
I - II - III
I - II - III
I - II - III
T
j
25 °C
25 °C
125 °C
25 °C
25 °C
125 °C
125 °C
125 °C
25 °C
MIN.
MAX.
MAX.
MIN.
MAX.
MAX.
MIN.
MIN.
2
850
20
40
500
ACST410 ACST435
10
1.0
0.2
25
60
1000
5
35
1.1
Unit
mA
V
V
mA
mA
V/µs
A/ms
A/ms
V
dV/dt
(2)
V
OUT
= 67 % V
DRM
, gate open
(dI/dt)
c(2)
Without snubber
(dI/dt)
c(2)
(dV/dt)
c
= 15 V/µs
V
CL
I
CL
= 0.1 mA, t
p
= 1 ms
1. Minimum I
GT
is guaranteed at 5% of I
GT
max
2. For both polarities of OUT pin referenced to COM pin
2/13
Doc ID 8766 Rev 5
ASCT4
Table 4.
Symbol
V
TM(1)
V
T0(1)
R
d(1)
I
DRM
I
RRM
I
OUT
= 5.6 A, t
p
= 500 µs
Threshold voltage
Dynamic resistance
V
OUT
= V
DRM
/ V
RRM
Characteristics
Static characteristics
Test conditions
T
j
= 25 °C
T
j
= 125 °C
T
j
= 125 °C
T
j
= 25 °C
T
j
= 125 °C
MAX.
MAX.
MAX.
MAX.
MAX.
Value
1.7
0.9
110
20
500
Unit
V
V
mΩ
µA
µA
1. For both polarities of OUT pin referenced to COM pin
Table 5.
Symbol
Thermal resistances
Parameter
Junction to ambient
TO-220FPAB
DPAK
TO-220FPAB
Value
60
°C/W
70
4.6
°C/W
DPAK
2.6
Unit
Rt
h(j-a)
Junction to ambient (soldered on 0.5 cm
2
copper pad)
Junction to case for full cycle sine wave conduction
R
th(j-c)
Figure 2.
Maximum power dissipation versus Figure 3.
on-state rms current
5
On-state rms current versus case
temperature (full cycle)
6
5
P(W)
α
= 180°
180°
IT(RMS)(A)
α=180°
4
DPAK
TO220FPAB
4
3
3
2
2
1
IT(RMS)(A)
1
TC (°C)
0
0
25
50
75
100
125
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Doc ID 8766 Rev 5
3/13
Characteristics
ASCT4
Figure 4.
On-state rms current versus
ambient temperature (free air
convection, full cycle)
Figure 5.
Relative variation of thermal
impedance versus pulse duration
2.0
IT(RMS)(A)
α=180°
TO-220FPAB
1.0E+00
K = [Zth / Rth]
Z
th(j-c)
DPAK
Z
th(j-a)
1.5
DPAK with copper
surface = 0.5 cm
2
1.0
1.0E-01
TO-220FPAB
0.5
Ta(°C)
0.0
0
25
50
75
100
125
1.0E-02
1.0E-03
1.0E-02
1.0E-01
1.0E+00
1.0E+01
Tp(s)
1.0E+02
1.0E+03
Figure 6.
Relative variation of gate trigger
current (I
GT
) and voltage (V
GT
)
versus junction temperature
Figure 7.
Relative variation of holding
current (I
H
) and latching current (I
L
)
versus junction temperature
3.0
2.5
2.0
1.5
IGT, VGT[Tj] / IGT, VGT[Tj = 25 °C]
(typical values)
IGT Q3
IGT Q1-Q2
2.5
IH, IL[Tj] / IH, IL[Tj = 25 °C]
(typical values)
2.0
1.5
1.0
1.0
0.5
V
GT
Q1-Q2-Q3
0.5
IL
IH
Tj(°C)
-50
-25
0
25
50
75
100
125
Tj(°C)
0.0
-50
0.0
-25
0
25
50
75
100
125
Figure 8.
Surge peak on-state current
versus number of cycles
Figure 9.
Non repetitive surge peak on-state
current and corresponding value of
I
2
t versus sinusoidal pulse width
35
30
ITSM(A)
1000
ITSM(A), I²t (A²s)
dl /dt limitation: 100 A / µs
Tj initial = 25 °C
t=20ms
25
20
15
Non repetitive
T
j
initial=25 °C
One cycle
100
ITSM
10
10
5
0
1
10
100
1000
Repetitive
T
C
=102°C
I²t
Number of cycles
1
0.01
t
p
(ms)
0.10
1.00
10.00
4/13
Doc ID 8766 Rev 5
ASCT4
Characteristics
Figure 10. On-state characteristics
(maximum values)
ITM(A)
Tjmax:
Vto = 0.90 V
Rd = 110 mΩ
Figure 11. Relative variation of critical rate of
decrease of main current (dI/dt)
c
versus junction temperature
(dI/dt)c [Tj] / (dl/dt)c [Tj = 125 °C]
8
7
6
5
100
10
4
3
2
Tj = 125 °C
Tj = 25 °C
1
VTM(V)
0
Tj(°C)
25
50
75
100
125
1
0
1
2
3
4
5
Figure 12. Relative variation of static dV/dt
immunity versus junction
temperature (gate open)
6
5
Figure 13. Relative variation of leakage
current versus junction
temperature
IDRM/IRRM [Tj; VDRM / VRRM] / IDRM/IRRM [Tj = 125 °C; 800 V]
1.0E+00
VDRM = VRRM = 800V
dV/dt [Tj] / dV/dt [Tj = 125 °C]
VD = VR = 536 V
Different blocking voltages
4
3
2
1
0
25
50
75
100
1.0E-02
VDRM = VRRM = 200 V
1.0E-01
VDRM = VRRM = 600 V
Tj(°C)
125
1.0E-03
25
Tj(°C)
50
75
100
125
Figure 14. Relative variation of the clamping
voltage (V
CL
) versus junction
temperature (minimum values)
1.15
1.10
1.05
1.00
0.95
Figure 15. Thermal resistance junction to
ambient versus copper surface
under tab
100
90
80
70
60
50
40
30
V
CL
[Tj] / V
CL
[Tj = 25 °C]
Rth(j-a)(°C/W)
Printed circuit board FR4,
copper thickness = 35 µm
DPAK
0.90
0.85
-50
20
Tj(°C)
-25
0
25
50
75
100
125
10
0
0
5
10
15
S
CU
(cm²)
20
25
30
35
40
Doc ID 8766 Rev 5
5/13
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