TRU050-GBLHA-49M4080000 datasheet, PDF

Datasheet> All Categories > Analog mixed-signal IC> The signal circuit> TRU050-GBLHA-49M4080000

TRU050-GBLHA-49M4080000: DescriptionPhase Locked Loop, CDSO16, SMD-16; CategoryAnalog mixed-signal IC The signal circuit; File Size172KB，14 Pages; ManufacturerVectron International, Inc.; Websitehttp://www.vectron.com/; Environmental Compliance

Download Datasheet Parametric View All

TRU050-GBLHA-49M4080000 Overview

Phase Locked Loop, CDSO16, SMD-16

TRU050-GBLHA-49M4080000 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Vectron International, Inc.
Parts packaging code	SOIC
package instruction	SOP,
Contacts	16
Reach Compliance Code	compli
Analog Integrated Circuits - Other Types	PHASE LOCKED LOOP
JESD-30 code	R-CDSO-G16
JESD-609 code	e4
length	20.32 mm
Humidity sensitivity level	1
Number of functions	1
Number of terminals	16
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	4.69 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Gold (Au) - with Nickel (Ni) barrie
Terminal form	GULL WING
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	40
width	7.88 mm

Preview

Download Datasheet

View All

TRU050

Complete VCXO based Phase-Locked Loop

Features

•

Output Frequencies to 65.536 MHz

•

5.0 V or 3.3Vdc Operation

•

Tri-State Output

•

Holdover on Loss of Signal Alarm

•

VCXO with CMOS Outputs

•

0/70° or –40/85°C Temperature Range

•

Ceramic SMD Package

•

RoHS/Lead Free Compliant

The TRU050, VCXO based PLL

Description

The VI TRU050 is a user-configurable crystal-based

PLL integrated circuit. It includes a digital phase

detector, op-amp, VCXO and additional integrated

functions for use in digital synchronization

applications. Loop filter software is available as well

SPICE models for circuit simulation.

Applications

•

Frequency Translation

•

Clock Smoothing

•

NRZ Clock Recovery

•

DSLAM, ADM, ATM, Aggregation, Optical

Switching/Routing, Base Station

•

Low Jitter PLL’s

Figure 1. TRU050 Block Diagram

Tel: 1-88-VECTRON-1

•

Web:

www.vectron.com

Page 1 of 14

Rev: 26Aug2008

Vectron International, 267 Lowell Rd, Hudson NH 03051-4916

TRU050, VCXO Based PLL

TRU050 Theory of Operation

Phase Detector

The phase detector has two buffered inputs, DATAIN and CLKIN, which are designed to switch at 1.4 volts.

DATAIN is designed to accept an NRZ data stream but may also be used for clock signals which have about

a 50% duty cycle. CLKIN is connected to OUT1 or OUT2, or a divided version of one of these outputs. CLKIN

and DATAIN and are protected by ESD diodes and should not exceed the power supply voltage or ground by

more than a few hundred millivolts.

The phase detector is basically a latched flip flop/exclusive-or gate/differential amplifier filter design to

produce a DC signal proportional to the phase between the CLKIN and DATAIN signals, see figure 4 for a

block diagram and figure 5 for a open loop transfer curve. This simplies the PLL design as the designer does

not have to filter narrow pulse signal to a DC level. Under locked conditions the rising edge CLKIN will be

centered in the middle of the DATAIN signal, see figure 6.

The phase detector gain is 0.53V/rad x data density for 5volt operation, and 0.35V/rad x data density for 3.3

volt operation. Data density = 1.0 for clock signals and is system dependent on coding and design for NRZ

signals, but 0.25 could be used as a starting point for data density.

The phase detector output is a DC signal for DATAIN frequencies greater than 1MHz but produces signficant

ripple when inputs are less than 200kHz. Additional filtering is required for low input frequency applications

such as 8kHz frequency translation, see figures 8 and 9.

Under closed loop conditions the active filter has a blocking capacitor which provides a very high DC gain, so

under normal locked conditions and input frequencies >1MHz, PHO will be about V

/2 and will not vary

signifigantly with changes in input frequency (within lock range). The control (voltage pin 1) will vary

according to the input frequency offset, but PHO will remain relatively constant.

Data In

(pin 7)

Clock In

(pin 9)

30 kΩ

20 kΩ

PHO

(pin 6)

Gain = 5 V / 2π

Gain = 2 / 3

Figure 4. Simplified Phase Detector Block Diagram

Vectron International, 267 Lowell Rd, Hudson NH 03051-4916

Page 4 of 14

Tel: 1-88-VECTRON-1

•

Web:

www.vectron.com

Rev: 26Aug2008

Recommended Resources

Thyristor magnetizer circuit one a

Nickel cadmium charger circuit diagram

Basic usage circuit diagram of LT1074

7.2V, 1.2A battery charging circuit diagram using ATC105

Cordless telephone ring current detection circuit

Computer motherboard circuit diagram 820 2_28

Problems using img_lib: [i=s] This post was last edited by dontium on 2015-1-23 13:25 [/i] This is the first time I use the img_lib library and want to use the IMG_ycbcr422p_rgb565 function in the library.The header file has...; pilot Analogue and Mixed Signal

Altera's 11.0 development software is out. Has anyone used it?: 11.0 is out, I installed it and tried it. It feels good, and I also used the DSP one. . . . . . Has anyone used it?Its driver package is very large, integrating QuartusII and NIOSII together. . . . Th...; shilaike FPGA/CPLD

Play with AT32F437 (4) --- Using SPI transmission as an example to explore the internal flash performance: [i=s]This post was last edited by RCSN on 2021-12-24 21:06[/i]According to the Yatli propaganda, AT32F437 can reach up to 4M flash and 512K ram. The model of the host is AT32F437VMT7, which happens to...; RCSN Domestic Chip Exchange

2015 China (Shanghai) International Rehabilitation Nursing and Health Exhibition: CIHE 2015 China (Shanghai) International Health Industry Exhibition 2015 China (Shanghai) International Health Industry Exhibition 2015 Shanghai International Rehabilitation Nursing and Health Mainten...; hjj7777777 Medical Electronics

Ask for a simple question about analog circuit: I cannot set the static operating point properly. According to the data, when IB is about 10uV and VCE is about 8V, the IC should be more than 4MA. Why is it inconsistent with the simulation result? I...; hy5239 Analog electronics

[Mil MYC-JX8MPQ review] + QT calls OpenCV library for testing: After we compile the OpenCV library, we still need to test it, and finally test it on the lower computer, so I chose to use QT for a cross-compilation and run OpenCV using the QT graphical interface. ...; 流行科技 Special Edition for Assessment Centres

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components