AGL1000V5-UCG144PP datasheet, PDF

Datasheet> All Categories > semiconductor> Programmable logic devices> AGL1000V5-UCG144PP

AGL1000V5-UCG144PP: DescriptionFPGA, 24576 CLBS, 1000000 GATES, 108 MHz, PBGA144; Categorysemiconductor Programmable logic devices; File Size6MB，264 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

Download Datasheet Parametric View All

AGL1000V5-UCG144PP Overview

FPGA, 24576 CLBS, 1000000 GATES, 108 MHz, PBGA144

AGL1000V5-UCG144PP Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	144
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	1.58 V
Minimum supply/operating voltage	1.14 V
Rated supply voltage	1.2 V
Processing package description	13 X 13 MM, 1.45 MM HEIGHT, 1 MM PITCH, HALOGEN FREE AND ROHS COMPLIANT, FBGA-144
Lead-free	Yes
EU RoHS regulations	Yes
state	ACTIVE
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	GRID ARRAY, LOW PROFILE
surface mount	Yes
Terminal form	BALL
Terminal spacing	1 mm
terminal coating	TIN SILVER COPPER
Terminal location	BOTTOM
Packaging Materials	PLASTIC/EPOXY
Temperature level	INDUSTRIAL
organize	24576 CLBS, 1000000 GATES
Maximum FCLK clock frequency	108 MHz
Number of configurable logic modules	24576
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Number of equivalent gate circuits	1.00E6

Preview

Download Datasheet

View All

Revision 27

DS0095

IGLOO Low Power Flash FPGAs

with Flash*Freeze Technology

Features and Benefits

Low Power

•

1.2 V to 1.5 V Core Voltage Support for Low Power

Supports Single-Voltage System Operation

5 µW Power Consumption in Flash*Freeze Mode

Low Power Active FPGA Operation

Flash*Freeze Technology Enables Ultra-Low Power

Consumption while Maintaining FPGA Content

• Easy Entry to / Exit from Ultra-Low Power Flash*Freeze Mode

• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS

3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X

†

and LVCMOS 2.5 V / 5.0 V Input

†

• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-

LVDS (AGL250 and above)

• Wide Range Power Supply Voltage Support per JESD8-B,

Allowing I/Os to Operate from 2.7 V to 3.6 V

• Wide Range Power Supply Voltage Support per JESD8-12,

Allowing I/Os to Operate from 1.14 V to 1.575 V

• I/O Registers on Input, Output, and Enable Paths

• Hot-Swappable and Cold-Sparing I/Os

‡

• Programmable Output Slew Rate

†

and Drive Strength

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the IGLOO Family

†

• Six CCC Blocks, One with an Integrated PLL

• Configurable Phase Shift, Multiply/Divide, Delay Capabilities,

and External Feedback

• Wide Input Frequency Range (1.5 MHz up to 250 MHz)

High Capacity

• 15K to 1 Million System Gates

• Up to 144 Kbits of True Dual-Port SRAM

• Up to 300 User I/Os

Reprogrammable Flash Technology

•

130-nm, 7-Layer Metal, Flash-Based CMOS Process

Instant On Level 0 Support

Single-Chip Solution

Retains Programmed Design When Powered Off

250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System

Performance

Clock Conditioning Circuit (CCC) and PLL

In-System Programming (ISP) and Security

• ISP Using On-Chip 128-Bit Advanced Encryption Standard

(AES) Decryption (except ARM

-enabled IGLOO

devices) via

JTAG (IEEE 1532–compliant)

†

• FlashLock

Designed to Secure FPGA Contents

Embedded Memory

• 1 kbit of FlashROM User Nonvolatile Memory

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit

†

RAM

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

• True Dual-Port SRAM (except ×18)

†

High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

ARM Processor Support in IGLOO FPGAs

Advanced I/O

• 700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above)

• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

IGLOO Devices

AGL015

ARM-Enabled IGLOO Devices

System Gates

15,000

Typical Equivalent Macrocells

128

VersaTiles (D-flip-flops)

384

Flash*Freeze Mode (typical, µW)

RAM kbits (1,024 bits)

–

4,608-Bit Blocks

–

FlashROM Kbits (1,024 bits)

AES-Protected ISP

–

Integrated PLL in CCCs

–

VersaNet Globals

I/O Banks

Maximum User I/Os

Package Pins

UC/CS

QFN

VQFP

FBGA

QN68

• M1 IGLOO Devices—Cortex

-M1 Soft Processor Available with

or without Debug

AGL030

30,000

256

768

–

AGL060 AGL125

60,000

512

1,536

Yes

125,000

1,024

3,072

Yes

133

CS196

QN132

VQ100

FG144

AGL250

M1AGL250

250,000

2,048

6,144

Yes

143

CS196

QN132

VQ100

FG144

AGL400

400,000

–

9,216

Yes

194

CS196

AGL600

M1AGL600

600,000

–

13,824

108

Yes

235

CS281

AGL1000

M1AGL1000

1,000,000

–

24,576

144

Yes

300

CS281

UC81, CS81 CS121

QN48, QN68,

QN132

VQ100

FG144, FG256, FG144, FG256, FG144, FG256,

FG484

Notes:

AGL015 is not recommended for new designs

AES is not available for ARM-enabled IGLOO devices.

AGL060 in CS121 does not support the PLL.

Six chip (main) and twelve quadrant global networks are available for AGL060 and above.

The M1AGL250 device does not support this package.

Package not available.

The

IGLOOe

datasheet and

IGLOOe FPGA Fabric User Guide

provide information on higher densities and additional features.

† AGL015 and AGL030 devices do not support this feature.

May 2016

‡ Supported only by AGL015 and AGL030 devices.

IGLOO Low Power Flash FPGAs

IGLOO Device Family Overview

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

IGLOO DC and Switching Characteristics

General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

Power Calculation Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-100

Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-106

Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-115

Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-118

Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-132

JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-133

Pin Descriptions

Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-1

3-2

3-4

3-5

Package Pin Assignments

UC81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

CS81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

CS121 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

CS196 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

CS281 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16

QN48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23

QN68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25

QN132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28

VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37

FG144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-42

FG256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53

FG484 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-63

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13

Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13

R ev i si o n 2 7

Recommended Resources

voltage rails and low quiescent current

Circuit diagram for detecting hypoxia

LASER310 learning machine circuit diagram

Detect hypoxia circuit with color sensor

Dual-Tracking regulated power supply circuit

Panasonic M12H power supply

Is there any way to use a 3.3V active buzzer with a 5V power supply?: Is there any way to use a 3.3V active buzzer with a 5V power supply?...; wangfuchong Discrete Device

Why does a 3D program developed with windml3.0 under vxworks5.5 have a black screen?: I followed Tony's instructions (setting up an environment for OpenGL programming under VxWorks) to compile the mesa4.0 source code and download the demo program to the target machine. However, when I ...; anyjun Real-time operating system RTOS

Interrupt issues: #include#include "vxWorks.h" #include#include#include "sysLib.h" #include#include "taskLib.h" SEM_ID syncSem; void inxxxx(void); void task1(void); void interruptxxxx(void); #define INUM_TO_IVEC(intNum...; hufangger Embedded System

Voltage Management: In general power management, overvoltage and undervoltage are subdivided. This is because the battery has high power and low power states. In addition, the situation of car batteries is special. From ...; yulzhu Analog electronics

Turning human skin into a touch panel~~~: In the next few years, will we no longer need mobile phones, but will our skin replace them?Use the palm as a touch screenThe system consists of an armband, a small projector and a computer. Here, the...; 老夫子 Creative Market

Help: About flash stick: Urgent, urgent, urgent, urgent, urgent, urgent... In life, we often see some flash sticks, which have different flash effects every time you press the button... I hope some expert can explain the prin...; 544725865 Analog electronics

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components