AGLN020V5-VQG100YPP datasheet, PDF

Datasheet> All Categories > semiconductor> Programmable logic devices> AGLN020V5-VQG100YPP

AGLN020V5-VQG100YPP: DescriptionFPGA, 520 CLBS, 20000 GATES, PBGA81; Categorysemiconductor Programmable logic devices; File Size7MB，148 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

Download Datasheet Parametric View All

AGLN020V5-VQG100YPP Overview

FPGA, 520 CLBS, 20000 GATES, PBGA81

AGLN020V5-VQG100YPP Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	81
Maximum operating temperature	70 Cel
Minimum operating temperature	-20 Cel
Maximum supply/operating voltage	1.58 V
Minimum supply/operating voltage	1.14 V
Rated supply voltage	1.2 V
Processing package description	5 X 5 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, CSP-81
Lead-free	Yes
EU RoHS regulations	Yes
state	ACTIVE
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
surface mount	Yes
Terminal form	BALL
Terminal spacing	0.5000 mm
terminal coating	NOT SPECIFIED
Terminal location	BOTTOM
Packaging Materials	PLASTIC/EPOXY
Temperature level	OTHER
organize	520 CLBS, 20000 GATES
Number of configurable logic modules	520
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Number of equivalent gate circuits	20000

Preview

Download Datasheet

View All

Revision 19

DS0110

IGLOO nano Low Power Flash FPGAs

with Flash*Freeze Technology

Features and Benefits

Low Power

•

nanoPower Consumption—Industry’s Lowest Power

1.2 V to 1.5 V Core Voltage Support for Low Power

Supports Single-Voltage System Operation

Low Power Active FPGA Operation

Flash*Freeze Technology Enables Ultra-Low Power

Consumption while Maintaining FPGA Content

• Easy Entry to / Exit from Ultra-Low Power Flash*Freeze Mode

• As Small as 3x3 mm in Size

High-Performance Routing Hierarchy

Advanced I/Os

• Segmented, Hierarchical Routing and Clock Structure

• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS

3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V

• Wide Range Power Supply Voltage Support per JESD8-B,

Allowing I/Os to Operate from 2.7 V to 3.6 V

• Wide Range Power Supply Voltage Support per JESD8-12,

Allowing I/Os to Operate from 1.14 V to 1.575 V

• I/O Registers on Input, Output, and Enable Paths

• Selectable Schmitt Trigger Inputs

• Hot-Swappable and Cold-Sparing I/Os

• Programmable Output Slew Rate and Drive Strength

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the IGLOO

Family

†

• Up to Six CCC Blocks, One with an Integrated PLL

• Configurable Phase Shift, Multiply/Divide, Delay

Capabilities, and External Feedback

• Wide Input Frequency Range (1.5 MHz up to 250 MHz)

• 1 kbit of FlashROM User Nonvolatile Memory

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

†

• True Dual-Port SRAM (except × 18 organization)

†

• Tj = -20°C to +85°C

Small Footprint Packages

Wide Range of Features

Reprogrammable Flash Technology

•

130-nm, 7-Layer Metal, Flash-Based CMOS Process

Instant On Level 0 Support

Single-Chip Solution

Retains Programmed Design When Powered Off

250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System

Performance

• 10,000 to 250,000 System Gates

• Up to 36 kbits of True Dual-Port SRAM

• Up to 71 User I/Os

Clock Conditioning Circuit (CCC) and PLL

In-System Programming (ISP) and Security

Embedded Memory

• ISP Using On-Chip 128-Bit Advanced Encryption Standard

(AES) Decryption via JTAG (IEEE 1532–compliant)

• FlashLock

Designed to Secure FPGA Contents

• 1.2 V Programming

Enhanced Commercial Temperature Range

AGLN060

AGLN030Z

IGLOO nano Devices

IGLOO nano-Z Devices

System Gates

Typical Equivalent Macrocells

VersaTiles (D-flip-flops)

Flash*Freeze Mode (typical, µW)

RAM Kbits (1,024 bits)

4,608-Bit Blocks

Secure (AES)

AGLN010 AGLN015

AGLN020

10,000

260

–

2,3

AGLN125

AGLN250

AGLN060Z

60,000

512

1,536

Yes

AGLN125Z

125,000

1,024

3,072

Yes

AGLN250Z

250,000

2,048

6,144

Yes

15,000

128

384

–

20,000

172

520

–

30,000

256

768

–

FlashROM Kbits (1,024 bits)

ISP

Integrated PLL in CCCs

VersaNet Globals

I/O Banks

Maximum User I/Os (packaged device)

Maximum User I/Os (Known Good Die)

–

† AGLN030 and smaller devices do not support this feature.

October 2015

Recommended Resources

One of the water shortage alarm circuits

YN5203 (anti-theft system) radio or infrared remote control decoding circuit

Small power inverter circuit

Telephone extension circuit with security function 1

Motorola V998 repair circuit diagram 1

15V, 600mA regulated power supply circuit

Can the simulator generated by pb5.0 be pinged by other PCs in the network?: Can the simulator's IP only be set to 192.168.131.x? If I want the simulator to be pingable from the outside, how should I set it? Thank you for your attention....; gundan Embedded System

Output three independent control digital cross-current constant voltage power supplies: [i=s]This post was last edited by Zeng in on 2015-2-11 16:55[/i] I made a power board with my classmates. The extra boards were made into finished products and sold. I bought a better development boar...; 曾经in Buy&Sell

Common semiconductor device model nomenclature: 1. National standard for naming common semiconductor device models The naming of common semiconductor device models consists of five parts. The first part uses numbers to indicate the number of electr...; 一世轮回 Integrated technical exchanges

After LM3S5B91 enters interruption, the middle port remains at a low level. What is going on?: After LM3S5B91 enters interrupt, the middle port keeps low level. What's going on? After entering the middle section, the interrupt is cleared, but the Io port still keeps low level. I am doing the ke...; clqsky Microcontroller MCU

Does anyone know of a package that looks the same as TO-92 but is even smaller?: The first row is 501S and the second row is 35L...; 帝国内 Power technology

The touch screen is offset after restarting: After calibration, the touch screen can work normally. Click point A, and the display also responds to point A. But after restarting, click point A, and point B responds. Regarding this phenomenon of ...; yleio Embedded System

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components