AGLN250V2-UC81 datasheet, PDF - EEWORLD Datasheet

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AGLN250V2-UC81: DescriptionFPGA, 520 CLBS, 20000 GATES, PBGA81; Categorysemiconductor Programmable logic devices; File Size7MB，148 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

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AGLN250V2-UC81 Overview

FPGA, 520 CLBS, 20000 GATES, PBGA81

AGLN250V2-UC81 Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	81
Maximum operating temperature	70 Cel
Minimum operating temperature	-20 Cel
Maximum supply/operating voltage	1.58 V
Minimum supply/operating voltage	1.14 V
Rated supply voltage	1.2 V
Processing package description	5 X 5 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, CSP-81
Lead-free	Yes
EU RoHS regulations	Yes
state	ACTIVE
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
surface mount	Yes
Terminal form	BALL
Terminal spacing	0.5000 mm
terminal coating	NOT SPECIFIED
Terminal location	BOTTOM
Packaging Materials	PLASTIC/EPOXY
Temperature level	OTHER
organize	520 CLBS, 20000 GATES
Number of configurable logic modules	520
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Number of equivalent gate circuits	20000

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Revision 19

DS0110

IGLOO nano Low Power Flash FPGAs

with Flash*Freeze Technology

Features and Benefits

Low Power

•

nanoPower Consumption—Industry’s Lowest Power

1.2 V to 1.5 V Core Voltage Support for Low Power

Supports Single-Voltage System Operation

Low Power Active FPGA Operation

Flash*Freeze Technology Enables Ultra-Low Power

Consumption while Maintaining FPGA Content

• Easy Entry to / Exit from Ultra-Low Power Flash*Freeze Mode

• As Small as 3x3 mm in Size

High-Performance Routing Hierarchy

Advanced I/Os

• Segmented, Hierarchical Routing and Clock Structure

• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS

3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V

• Wide Range Power Supply Voltage Support per JESD8-B,

Allowing I/Os to Operate from 2.7 V to 3.6 V

• Wide Range Power Supply Voltage Support per JESD8-12,

Allowing I/Os to Operate from 1.14 V to 1.575 V

• I/O Registers on Input, Output, and Enable Paths

• Selectable Schmitt Trigger Inputs

• Hot-Swappable and Cold-Sparing I/Os

• Programmable Output Slew Rate and Drive Strength

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the IGLOO

Family

†

• Up to Six CCC Blocks, One with an Integrated PLL

• Configurable Phase Shift, Multiply/Divide, Delay

Capabilities, and External Feedback

• Wide Input Frequency Range (1.5 MHz up to 250 MHz)

• 1 kbit of FlashROM User Nonvolatile Memory

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

†

• True Dual-Port SRAM (except × 18 organization)

†

• Tj = -20°C to +85°C

Small Footprint Packages

Wide Range of Features

Reprogrammable Flash Technology

•

130-nm, 7-Layer Metal, Flash-Based CMOS Process

Instant On Level 0 Support

Single-Chip Solution

Retains Programmed Design When Powered Off

250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System

Performance

• 10,000 to 250,000 System Gates

• Up to 36 kbits of True Dual-Port SRAM

• Up to 71 User I/Os

Clock Conditioning Circuit (CCC) and PLL

In-System Programming (ISP) and Security

Embedded Memory

• ISP Using On-Chip 128-Bit Advanced Encryption Standard

(AES) Decryption via JTAG (IEEE 1532–compliant)

• FlashLock

Designed to Secure FPGA Contents

• 1.2 V Programming

Enhanced Commercial Temperature Range

AGLN060

AGLN030Z

IGLOO nano Devices

IGLOO nano-Z Devices

System Gates

Typical Equivalent Macrocells

VersaTiles (D-flip-flops)

Flash*Freeze Mode (typical, µW)

RAM Kbits (1,024 bits)

4,608-Bit Blocks

Secure (AES)

AGLN010 AGLN015

AGLN020

10,000

260

–

2,3

AGLN125

AGLN250

AGLN060Z

60,000

512

1,536

Yes

AGLN125Z

125,000

1,024

3,072

Yes

AGLN250Z

250,000

2,048

6,144

Yes

15,000

128

384

–

20,000

172

520

–

30,000

256

768

–

FlashROM Kbits (1,024 bits)

ISP

Integrated PLL in CCCs

VersaNet Globals

I/O Banks

Maximum User I/Os (packaged device)

Maximum User I/Os (Known Good Die)

–

† AGLN030 and smaller devices do not support this feature.

October 2015

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