Features
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Programmable 4,194,304 x 1 and 8,388,608 x 1-bit Serial Memories Designed to Store
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Configuration Programs for Field Programmable Gate Arrays (FPGAs)
3.3V Output Capability
5V Tolerant I/O Pins
Program Support using the Atmel ATDH2200E System or Industry Third Party
Programmers
In-System Programmable (ISP) via 2-wire Bus
Simple Interface to SRAM FPGAs
Compatible with Atmel AT40K and AT94K Devices, Altera
®
FLEX
®
, Excalibur
™
, Stratix
®
,
Cyclone
™
and APEX
™
Devices
Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
Low-power CMOS FLASH Process
Available in 8-lead LAP, 20-lead PLCC and 32-lead TQFP Packages
Emulation of Atmel’s AT24CXXX Serial EEPROMs
Low-power Standby Mode
Single Device Capable of Holding 4 Bit Stream Files Allowing Simple System
Reconfiguration
Fast Serial Download Speeds up to 33 MHz
Endurance: 5,000 Write Cycles Typical
Green (Lead/Halide-free/ROHS compliant) Packages
FPGA
Configuration
Flash Memory
AT17F040A
AT17F080A
1. Description
The AT17FxxxA Series of In-System Programmable Configuration PROMs (Configu-
rators) provide an easy-to-use, cost-effective configuration memory for Field
Programmable Gate Arrays. The AT17FxxxA Series device is packaged in the 8-lead
LAP, 20-lead PLCC and 32-lead TQFP, see
Table 1-1.
The AT17FxxxA Series Con-
figurator uses a simple serial-access procedure to configure one or more FPGA
devices.
The AT17FxxxA Series Configurators can be programmed with industry-standard pro-
grammers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.
Table 1-1.
Package
8-lead LAP
20-lead PLCC
32-lead TQFP
AT17FxxxA Series Packages
AT17F040A
Yes
Yes
Yes
AT17F080A
Yes
Yes
Yes
2823D–CNFG–2/08
2. Pin Configuration
8-lead LAP
DATA
DCLK
RESET/OE
nCS
1
2
3
4
8
7
6
5
VCC
SER_EN
(A2) nCASC
GND
20-lead PLCC
3
2
1
20
19
32-lead TQFP
NC
DATA
NC
VCC
NC
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
NC
DATA
NC
NC
NC
VCC
NC
NC
nCS
GND
PAGESEL0
(A2) nCASC
NC
9
10
11
12
13
DCLK
NC
NC
PAGESEL1
RESET/OE
4
5
6
7
8
18
17
16
15
14
SER_EN
NC
PAGE_EN
READY
NC
NC
DCLK
NC
NC
NC
PAGESEL1
RESET/OE
NC
1
2
3
4
5
6
7
8
NC
SER_EN
NC
PAGE_EN
READY
NC
NC
NC
2
AT17F040A/080A
2823D–CNFG–2/08
NC
nCS
NC
GND
NC
PAGESEL0
(A2) nCASC
NC
AT17F040A/080A
3. Block Diagram
READY
Power-on
Reset
Reset
Clock/Oscillator
Logic
DCLK
PAGE_EN
PAGESEL0
PAGESEL1
Config. Page
Select
nCASC(A2)
Serial Download Logic
2-wire Serial Programming
DATA
Flash
Memory
CE/WE/OE
Data
Address
nCS
Control Logic
RESET/OE
SER_EN
4. Device Description
The control signals for the configuration memory device (nCS, RESET/OE and DCLK) interface
directly with the FPGA device control signals. All FPGA devices can control the entire configura-
tion process and retrieve data from the configuration device without requiring an external
intelligent controller.
The RESET/OE and nCS pins control the tri-state buffer on the DATA output pin and enable the
address counter. When RESET/OE is driven Low, the configuration device resets its address
counter and tri-states its DATA pin. The nCS pin also controls the output of the AT17FxxxA
Series Configurator. If nCS is held High after the RESET/OE reset pulse, the counter is disabled
and the DATA output pin is tri-stated. When OE is subsequently driven High, the counter and the
DATA output pin are enabled. When RESET/OE is driven Low again, the address counter is
reset and the DATA output pin is tri-stated, regardless of the state of nCS.
When the configurator has driven out all of its data and nCASC is driven Low, the device tri-
states the DATA pin to avoid contention with other configurators. Upon power-up, the address
counter is automatically reset.
3
2823D–CNFG–2/08
5. Pin Description
Table 5-1.
Pin Description
AT17F040A/080A
Name
DATA
DCLK
PAGE_EN
PAGESEL0
PAGESEL1
RESET/
OE
nCS
GND
nCASC
A2
READY
SER_EN
V
CC
I/O
I/O
I
I
I
I
I
I
–
O
20
PLCC
2
4
16
11
7
8
9
10
12
32
TQFP
31
2
21
14
6
7
10
12
15
20
23
27
I
O
I
–
15
18
20
5.1
DATA
(1)
Three-state DATA output for FPGA configuration. Open-collector bi-directional pin for configura-
tion programming.
5.2
DCLK
(1)
Three-state clock. Functions as an input when the Configurator is in programming mode (i.e.
SER_EN is Low) and as an output during FPGA configuration.
5.3
PAGE_EN
(2)
Input used to enable page download mode. When PAGE_EN is high the configuration download
address space is partitioned into 4 equal pages. This gives users the ability to easily store and
retrieve multiple configuration bitstreams from a single configuration device. This input works in
conjunction with the PAGESEL inputs. PAGE_EN must be remain low if paging is not desired.
When SER_EN is Low (ISP mode) this pin has no effect.
Notes:
1. This pin has an internal 20 kΩ pull-up resistor.
2. This pin has an internal 30 kΩ pull-down resistor.
4
AT17F040A/080A
2823D–CNFG–2/08
AT17F040A/080A
5.4
PAGESEL[1:0]
(2)
Page select inputs. Used to determine which of the 4 memory pages are targeted during a serial
configuration download. The address space for each of the pages is shown in
Table 5-2.
When
SER_EN is Low (ISP mode) these pins have no effect.
Table 5-2.
Address Space
AT17F040A (4 Mbits)
00000 – 0FFFFh
10000 – 1FFFFh
20000 – 2FFFFh
30000 – 3FFFFh
00000 – 3FFFFh
AT17F080A (8 Mbits)
00000 – 1FFFFh
20000 – 3FFFFh
40000 – 5FFFFh
60000 – 7FFFFh
00000 – 7FFFFh
Paging Decodes
PAGESEL = 00, PAGE_EN = 1
PAGESEL = 01, PAGE_EN = 1
PAGESEL = 10, PAGE_EN = 1
PAGESEL = 11, PAGE_EN = 1
PAGESEL = XX, PAGE_EN = 0
5.5
RESET/OE
(1)
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low level on
RESET/OE resets both the address and bit counters. A High level (with nCS Low) enables the
data output driver.
5.6
nCS
(1)
Chip Enable input (active Low). A Low level (with OE High) allows DCLK to increment the
address counter and enables the data output driver. A High level on nCS disables both the
address and bit counters and forces the device into a low-power standby mode. Note that this
pin will
not
enable/disable the device in the 2-wire Serial Programming mode (SER_EN Low).
5.7
GND
Ground pin. A 0.2 µF decoupling capacitor between V
CC
and GND is recommended.
5.8
nCASC
Cascade Select Output (when SER_EN is High). This output goes Low when the internal
address counter has reached its maximum value. If the PAGE_EN input is set High, the maxi-
mum value is the highest address in the selected partition. The PAGESEL[1:0] inputs are used
to make the 4 partition selections. If the PAGE_EN input is set Low, the device is not partitioned
and the address maximum value is the highest address in the device, see
Table 5-2 on page 5.
In a daisy chain of AT17FxxxA Series devices, the nCASC pin of one device must be connected
to the nCS input of the next device in the chain. It will stay Low as long as nCS is Low and OE is
High. It will then follow nCS until OE goes Low; thereafter, nCASC will stay High until the entire
EEPROM is read again.
5.9
A2
(1)
Device selection input, (when SER_EN Low). The input is used to enable (or chip select) the
device during programming (i.e., when SER_EN is Low). Refer to the AT17FxxxA Programming
Specification available on the Atmel web site for additional details.
Notes:
1. This pin has an internal 20 k pull-up resistor.
2. This pin has an internal 30 kΩ pull-down resistor.
5
2823D–CNFG–2/08
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