AX500-2FG896I datasheet, PDF - EEWORLD Datasheet

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AX500-2FG896I: DescriptionFPGA, 12096 CLBS, 1000000 GATES, 649 MHz, PBGA896; Categorysemiconductor Programmable logic devices; File Size2MB，226 Pages; ManufacturerActel; Websitehttp://www.actel.com/

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AX500-2FG896I Overview

FPGA, 12096 CLBS, 1000000 GATES, 649 MHz, PBGA896

AX500-2FG896I Parametric

Parameter Name	Attribute value
Number of terminals	896
Minimum operating temperature	0.0 Cel
Maximum operating temperature	70 Cel
Processing package description	1 MM PITCH, FBGA-896
each_compli	Yes
state	Active
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
clock_frequency_max	649 MHz
The maximum delay of a CLB module	0.9900 ns
jesd_30_code	S-PBGA-B896
jesd_609_code	e0
moisture_sensitivity_level	3
Number of configurable logic modules	12096
Number of equivalent gate circuits	1.00E6
organize	12096 CLBS, 1000000 GATES
Packaging Materials	PLASTIC/EPOXY
ckage_code	BGA
packaging shape	SQUARE
Package Size	GRID ARRAY
eak_reflow_temperature__cel_	225
qualification_status	COMMERCIAL
seated_height_max	2.44 mm
Rated supply voltage	1.5 V
Minimum supply voltage	1.42 V
Maximum supply voltage	1.58 V
surface mount	YES
Craftsmanship	CMOS
Temperature level	COMMERCIAL
terminal coating	TIN LEAD
Terminal form	BALL
Terminal spacing	1 mm
Terminal location	BOTTOM
ime_peak_reflow_temperature_max__s_	30
length	31 mm
width	31 mm
dditional_feature	1000000 SYSTEM GATES AVAILABLE

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v2.7

Axcelerator Family FPGAs

u e

™

Leading-Edge Performance

•

350+ MHz System Performance

500+ MHz Internal Performance

High-Performance Embedded FIFOs

700 Mb/s LVDS Capable I/Os

Up to 2 Million Equivalent System Gates

Up to 684 I/Os

Up to 10,752 Dedicated Flip-Flops

Up to 295 kbits Embedded SRAM/FIFO

Manufactured on Advanced 0.15

μm

CMOS Antifuse

Process Technology, 7 Layers of Metal

Single-Chip, Nonvolatile Solution

Up to 100% Resource Utilization with 100% Pin Locking

1.5V Core Voltage for Low Power

Footprint Compatible Packaging

Flexible, Multi-Standard I/Os:

– 1.5V, 1.8V, 2.5V, 3.3V Mixed Voltage Operation

– Bank-Selectable I/Os – 8 Banks per Chip

– Single-Ended I/O Standards: LVTTL, LVCMOS, 3.3V

PCI, and 3.3V PCI-X

– Differential I/O Standards: LVPECL and LVDS

AX125

125,000

82,000

672

1,344

18,432

168

504

180

Specifications

•

Features

•

Voltage-Referenced I/O Standards: GTL+, HSTL

Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2

– Registered I/Os

– Hot-Swap Compliant I/Os (except PCI)

– Programmable Slew Rate and Drive Strength on

Outputs

– Programmable Delay and Weak Pull-Up/Pull-Down

Circuits on Inputs

Embedded Memory:

– Variable-Aspect 4,608-bit RAM Blocks (x1, x2, x4,

x9, x18, x36 Organizations Available)

– Independent, Width-Configurable Read and Write Ports

– Programmable Embedded FIFO Control Logic

Segmentable Clock Resources

Embedded Phase-Locked Loop:

– 14-200 MHz Input Range

– Frequency Synthesis Capabilities up to 1 GHz

Deterministic, User-Controllable Timing

Unique In-System Diagnostic and Debug Capability

with Actel Silicon Explorer II

Boundary-Scan Testing Compliant with IEEE Standard

1149.1 (JTAG)

FuseLock

Secure Programming Technology

Prevents Reverse Engineering and Design Theft

–

Table 1-1 •

Axcelerator Family Product Profile

Device

Capacity (in Equivalent System Gates)

Typical Gates

Modules

Combinatorial (C-cells)

Maximum Flip-Flops

Embedded RAM/FIFO

Number of Core RAM Blocks

Total Bits of Core RAM

Clocks (Segmentable)

Hardwired

Routed

PLLs

I/Os

I/O Banks

Maximum User I/Os

Maximum LVDS Channels

Total I/O Registers

Package

CSP

PQFP

BGA

FBGA

CQFP

CCGA

AX250

250,000

154,000

1,408

2,816

55,296

248

124

744

AX500

500,000

286,000

2,688

5,376

73,728

336

168

1,008

AX1000

1,000,000

612,000

6,048

12,096

165,888

516

258

1,548

AX2000

2,000,000

1,060,000

10,752

21,504

294,912

684

342

2,052

208

256, 324

256, 484

208, 352

208

484, 676

208, 352

729

484, 676, 896

352

624

896, 1152

352

624

November 2008

*See Actel’s website for the latest version of the datasheet.

Axcelerator Family FPGAs

Table of Contents

General Description

Device Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Programmable Interconnect Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Logic Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

I/O Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Low Power (LP) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

In-System Diagnostic and Debug Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

Detailed Specifications

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

Voltage-Referenced I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32

Differential Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39

Module Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43

Routing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50

Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-55

Axcelerator Clock Management System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63

Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-72

Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-89

Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-91

Package Pin Assignments

180-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

729-Pin PBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12

324-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22

676-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36

896-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49

v2.7

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