DSC557-03
Crystal-less Two Output PCIe Gen1/2/3 Clock Generator
General Description
The DSC557-03 is a crystal-less, two output
PCI express clock generator meeting Gen1,
Gen2, and Gen3 specifications. The clock
generator uses proven silicon MEMS
technology to provide 100MHz* differential
output clocks with excellent jitter and
stability over a wide range of supply
voltages and temperatures. By eliminating
the external quartz crystal, the DSSC557-03
significantly
enhances
reliability
and
accelerates product development, while
meeting stringent clock performance criteria
for a variety of communications, storage,
and networking applications.
DSC557-03 has an Output Enable / Disable
feature allowing it to disable the outputs
when OE is low. The device is available in
two
different
packages;
a
“drop-in”
replacement 16 pin TSSOP or a space
saving 14 pin QFN (77% less board space).
Additional output formats are also available
in any combination of LVPECL, LVDS, and
HCSL.
Features
Meets PCIe Gen1, Gen2 & Gen3 specs.
Available Output Formats:
o
o
o
o
o
HCSL, LVPECL, or LVDS
HCSL/LVPECL, HCSL/LVDS, LVPECL/LVDS
Ext. Industrial: -40° to 105° C
Industrial: -40° to 85° C
Ext. commercial: -20° to 70° C
Wide Temperature Range
Supply Range of 2.25 to 3.6 V
Low Power Consumption
o
o
o
o
30% lower than competing devices
Qualified to MIL-STD-883
16 TSSOP
14 QFN
Excellent Shock & Vibration Immunity
Available Footprints:
Lead Free & RoHS Compliant
Block Diagram
Control Circuitry
CLK0+
CLK0-
Applications
Communications/Networking
Output
Control
and
Divider
MEMS
PLL
OE
CLK1-
CLK1+
o
o
o
o
o
Ethernet
1G, 10GBASE-T/KR/LR/SR, and FcoE
Routers and Switches
Gateways, VoIP, Wireless AP’s
Passive Optical Networks
*
Clk0+/- and Clk1+/- are 100 MHz as per PCIe
standards. For other frequencies, please
contact the factory.
Storage
o
SAN, NAS, SSD, JBOD
Embedded Applications
o
Industrial, Medical, and Avionics
o
Security Systems and Office
Automation
o
Digital Sinage, POS and others
Consumer Electronics
o
Smart TV, Bluray, STB
_____________________________________________________________________________________________________________________________ _________________
DSC557-03
Page 1
MK-QB-P-D-120917-01-2
DSC557-03
Crystal-less Two Output PCIe Gen1/2/3 Clock Generator
Specifications
(Unless specified otherwise: T=25° C, VDD =3.3V)
Parameter
Supply Voltage
1
Supply Current
Supply Current
2
(Two HCSL Outputs)
Frequency Stability
Startup Time
3
Input Logic Levels
Input logic high
Input logic low
Output Disable Time
4
Output Enable Time
Pull-Up Resistor
2
V
DD
I
DD
I
DD
Δf
t
SU
V
IH
V
IL
t
DA
t
EN
Pull-up on OE pin
40
0.75xV
DD
-
EN pin low – outputs are
disabled
EN pin high – outputs are
enabled
R
L
=50 Ω, F
O1
=F
O2
=100 MHz
Includes frequency variations
due to initial tolerance, temp.
and power supply voltage
Condition
Min.
2.25
Typ.
21
60
Max.
3.6
23
Unit
V
mA
mA
±100
±50
5
-
0.25xV
DD
5
20
ppm
ms
V
ns
ns
kΩ
HCSL Outputs
6
Parameter
Output Logic Levels
Output logic high
Output logic low
Pk to Pk Output Swing
Output Transition time
Rise Time
Fall Time
Frequency
Output Duty Cycle
Period Jitter
5
4
Condition
V
OH
V
OL
R
L
=50Ω
Single-Ended
t
R
t
F
f
0
SYM
J
PER
R
J
D
J
T
J
J
RMS-CCHF
J
RMS-CCLF
J
RMS-CC
20% to 80%
R
L
=50Ω, C
L
= 2pF
Single Frequency
Differential
F
O1
=F
O2
=100 MHz
PCIe Gen 1.1
T
J
=D
J
+ 14.069 x R
J
(BER 10-12)
PCIe Gen 1.1
T
J
=D
J
+ 14.069 x R
J
(BER 10-12)
PCIe Gen 2.1, 1.5 MHz to
Nyquist
PCIe Gen 2.1, 10 kHz to 1.5 MHz
PCIe Gen 3.0
PCIe Gen 2.1, 1.5 MHz to
Nyquist
PCIe Gen 2.1, 10 kHz to 1.5 MHz
PCIe Gen 3.0
Min.
0.725
-
Typ.
Max.
-
0.1
Unit
V
mV
750
200
2.3
48
2.5
0.540
0.832
8.536
0.458
0.030
0.165
0.561
1.778
0.147
41.9
8
86.0
8
3.1
8
3.0
8
1.0
8
4.0
8
7.5
8
1.0
8
100
7
400
460
52
ps
MHz
%
ps
RMS
Ps
RMS
Jitter, Phase
(Common Clock
Architecture)
ps
p-p
ps
RMS
ps
RMS
ps
RMS
ps
RMS
ps
RMS
ps
RMS
Integrated Phase Noise
(Data Clock
Architecture)
J
RMS-DCHF
J
RMS-DCLF
J
RMS-DC
Notes:
1. V
DD
should be filtered with 0.01uf capacitor.
2. Output is enabled if OE pin is floated or not connected.
3. t
su
is time to 100PPM stable output frequency after V
DD
is applied and outputs are enabled.
4. Output Waveform and Connection Diagram define the parameters.
5. Period Jitter includes crosstalk from adjacent output.
6. Contact
Sales@Discera.com
for alternate output options (LVPECL, LVDS, LVCMOS).
7. Contact
Sales@Discera.com
for alternative frequency options
8. Jitter limits established by Gen 1.1, Gen 2.1, and Gen 3.0 PCIe standards.
_____________________________________________________________________________________________________________________________ _________________
DSC557-03
Page 2
MK-QB-P-D-120917-01-2
DSC557-03
Crystal-less Two Output PCIe Gen1/2/3 Clock Generator
Absolute Maximum Ratings
Item
Supply Voltage
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
ESD
HBM
MM
CDM
Min
-0.3
-0.3
-
-55
-
-
Max
+4.0
V
DD
+0.3
+150
+150
+260
4000
400
1500
Unit
V
V
°C
°C
°C
V
Condition
40sec max.
Solder Reflow Profile
20-40
Sec
Temperature (°C)
217
°
C
200
°
C
.
ax
3C
/
Se
cM
ax
60-150
Sec
260
°
C
.
S
6C/
6C/
6C/
c
c
ec
Ma
Ma
Ma
150
°
C
3C
/
Se
60-180
Sec
cM
Reflow
.
.
x.
Pre heat
8 min max
Cool
Time
25
°
C
14 QFN
MSL 1 @ 260°C refer to JSTD-020C
16 TSSOP MSL 3 @ 260°C refer to JSTD-020C
Ramp-Up Rate (200°C to Peak Temp)
3°C/Sec Max.
Preheat Time 150°C to 200°C
60-180 Sec
Time maintained above 217°C
60-150 Sec
Peak Temperature
255-260°C
Time within 5°C of actual Peak
20-40 Sec
Ramp-Down Rate
6°C/Sec Max.
Time 25°C to Peak Temperature
8 min Max.
_____________________________________________________________________________________________________________________________ _________________
DSC557-03
Page 3
MK-QB-P-D-120917-01-2
DSC557-03
Crystal-less Two Output PCIe Gen1/2/3 Clock Generator
Pin Diagram (16 TSSOP)
Connection Diagram
(16 TSSOP Two HCSL Outputs)
NC
NC
NC
NC
NC
OE
VSS
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
CLK0+
CLK0-
NC
NC
CLK1-
CLK1+
NC
+
Enable
-
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Ropt
0.01 uF
+
VDD
-
CLK0+
CLK0-
50
W
50
W
CLK1-
CLK1+
50
W
50
W
16-TSSOP (173 mil)
(5.1 x 6.8 mm)
Ropt 22W
-
33
W
optional
Pin Description (16 TSSOP)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
9
NC
NC
NC
NC
NC
OE
VSS
NC
NC
CLK1+
CLK1-
NC
NC
CLK0-
CLK0+
VDD
Pin Type
NA
NA
NA
NA
NA
I
Power
NA
NA
O
O
NA
NA
O
O
Power
Description
No connect
No connect
No connect
No connect
No connect
Output Enable; active high
Ground
No connect
No connect
True output of differential pair
Complement output of differential pair
No connect
No connect
Complement output of differential pair
True output of differential pair
Power Supply
_____________________________________________________________________________________________________________________________ _________________
DSC557-03
Page 4
MK-QB-P-D-120917-01-2
DSC557-03
Crystal-less Two Output PCIe Gen1/2/3 Clock Generator
Pin Diagram (14 QFN)
Connection Diagram
(14 QFN Two HCSL Outputs)
VDD1
VDD0
0.01 uF
0.01 uF
+
VDD
-
NC
14
OE
NC
NC
VSS
1
2
3
4
5
NC
13
12
11
10
9
8
CLK0+
CLK0-
CLK1-
CLK1+
+
Enable
-
1
2
3
4
14
13
12
11
10
9
8
50
W
50
W
CLK0+
CLK0-
5
6
7
Ropt
CLK1-
CLK1+
6
NC
7
NC
Ropt 22W
-
33
W
optional
50
W
50
W
14 QFN 3.2x2.5mm
Pin Description (14 QFN)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin Name
OE
NC
NC
VSS
NC
NC
NC
CLK1+
CLK1-
CLK0-
CLK0+
VDD1
VDD0
NC
Pin
Type
I
NA
NA
Power
NA
NA
NA
O
O
O
O
Power
Power
NA
Description
Output Enable; active high
Ground recommended or leave as a NC
Ground recommended or leave as a NC
Ground
Ground recommended or leave as a NC
Ground recommended or leave as a NC
Ground recommended or leave as a NC
True output of differential pair
Complement output of differential pair
Complement output of differential pair
True output of differential pair
Power Supply for Core and Output 1 (CLK0+/-)
Power Supply for Output 0 (CLK1+/-)
Ground recommended or leave as a NC
_____________________________________________________________________________________________________________________________ _________________
DSC557-03
Page 5
MK-QB-P-D-120917-01-2
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