Datasheet
Serial EEPROM Series Automotive EEPROM
105℃ Operation I
2
C BUS EEPROM (2-Wire)
BR24Axxx-WM
(1K 2K 4K 8K 16K 32K 64K)
●General
Description
BR24Axxx-WM is a serial EEPROM of I
2
C BUS interface method.
●Features
Completely conforming to the world standard I
2
C BUS.
All controls available by 2 ports of serial clock
(SCL) and serial data (SDA)
Wide temperature range -40℃ to +105℃
Other devices than EEPROM can be connected to
the same port, saving microcontroller port
2.5V to 5.5V single power source operation most
suitable for battery use
Page write mode useful for initial value write at
factory shipment
Auto erase and auto end function at data rewrite
Low current consumption
At write operation (5V)
: 1.2mA (Typ.)
*1
At read operation (5V)
: 0.2mA (Typ.)
At standby condition (5V) : 0.1μA (Typ.)
Write mistake prevention function
Write (write protect) function added
Write mistake prevention function at low voltage
Data rewrite up to 1,000,000 times(Ta≦25℃）
Data kept for 40 years(Ta≦25℃）
Noise filter built in SCL / SDA terminal
Shipment data all address FFh
*1 BR24A32-WM, BR24A64-WM : 1.5mA
●Packages
W(Typ.) x D(Typ.) x H(Max.)
SOP8
5.00mm x 6.20mm x 1.71mm
SOP- J8
4.90mm x 6.00mm x 1.65mm
MSOP8
2.90mm x 4.00mm x 0.90mm
AEC-Q100 Qualified
●Page
write
Number of Pages
Product
number
8Byte
BR24A01A-WM
BR24A02-WM
16Byte
BR24A04-WM
BR24A08-WM
BR24A16-WM
32Byte
BR24A32-WM
BR24A64-WM
●BR24Axxx-WM
Capacity
Bit format
1Kbit
128×8
2Kbit
256×8
4Kbit
512×8
8Kbit
1K×8
16Kbit
2K×8
32Kbit
4K×8
64Kbit
8K×8
Type
BR24A01A-WM
BR24A02-WM
BR24A04-WM
BR24A08-WM
BR24A16-WM
BR24A32-WM
BR24A64-WM
Power source voltage
2.5V to 5.5V
2.5V to 5.5V
2.5V to 5.5V
2.5V to 5.5V
2.5V to 5.5V
2.5V to 5.5V
2.5V to 5.5V
SOP8
●
●
●
●
●
●
●
SOP-J8
●
●
●
●
●
MSOP8
●
○Product
structure: Silicon monolithic integrated circuit
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©2012 ROHM Co., Ltd. All rights reserved.
TSZ22111½14½001
○This
product is not designed protection against radioactive rays
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TSZ02201-0R1R0G100140-1-2
29.Jan.2018 Rev.003
BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)
●Absolute
Maximum Ratings
(Ta=25℃)
Parameter
Supply Voltage
Power Dissipation
Storage Temperature
Operating Temperature
Terminal Voltage
Symbol
V
CC
Pd
Tstg
Topr
‐
Ratings
-0.3 to +6.5
0.45 (SOP8)
0.45 (SOP-J8)
0.31 (MSOP8)
-65 to +125
-40 to +105
-0.3 to V
CC
+1.0
℃
℃
V
W
Unit
V
When using at Ta=25℃ or higher 4.5mW to be reduced per 1℃.
When using at Ta=25℃ or higher 4.5mW to be reduced per 1℃.
When using at Ta=25℃ or higher 3.1mW to be reduced per 1℃.
Remarks
●Memory
cell characteristics (V
CC
=2.5V to 5.5V)
Parameter
Number of data rewrite times
*1
Data hold years
*1
○Shipment
data all address FFh
*1Not 100% TESTED
Min.
1,000,000
100,000
40
10
Limits
Typ.
-
-
-
-
Max
-
-
-
-
Unit
Times
Years
Conditions
Ta≦25℃
Ta≦105℃
Ta≦25℃
Ta≦105℃
●Recommended
Operating Ratings
Parameter
Symbol
Power source voltage
V
CC
Input voltage
V
IN
Ratings
2.5 to 5.5
0 to V
CC
Unit
V
●Electrical
characteristics (Unless otherwise specified, Ta=-40℃ to +105℃, V
CC
=2.5V to 5.5V)
Limits
Parameter
Symbol
Unit
Conditions
Min.
Typ.
Max.
“HIGH” input voltage
V
IH
0.7 V
CC
-
-
V
“LOW” input voltage
V
IL
-
-
0.3 V
CC
V
“LOW” output voltage 1
V
OL
-
-
0.4
V
I
OL
=3.0mA (SDA)
Input leak current
I
LI
-1
-
1
μA
V
IN
=0V to V
CC
Output leak current
I
LO
-1
-
1
μA
V
OUT
=0V to V
CC
, (SDA)
*1
2.0
V
CC
=5.5V,f
SCL
=400kHz, t
WR
=5ms,
I
CC1
-
-
mA
*2
Byte write, Page write
3.0
Current consumption
V
CC
=5.5V,f
SCL
=400kHz
I
CC2
-
-
0.5
mA
Random read, current read, sequential read
V
CC
=5.5V, SDA・SCL= V
CC
Standby current
I
SB
-
-
2.0
μA
A0, A1, A2=GND, WP=GND
*1 BR24A01A/02/04/08/16-WM, *2 BR24A32/64-WM
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TSZ22111・15・001
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TSZ02201-0R1R0G100140-1-2
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BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)
●Operating
timing characteristics (Unless otherwise specified, Ta=
-
40℃ to +105℃, V
CC
=2.5V to 5.5V)
FAST-MODE
STANDARD-MODE
2.5V≦V
CC
≦5.5V
2.5V≦V
CC
≦5.5V
Parameter
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
SCL frequency
f
SCL
-
-
400
-
-
100
Data clock “HIGH“ time
t
HIGH
0.6
-
-
4.0
-
-
Data clock “LOW“ time
t
LOW
1.2
-
-
4.7
-
-
*1
SDA, SCL rise time
t
R
-
-
0.3
-
-
1.0
*1
SDA, SCL fall time
tF
-
-
0.3
-
-
0.3
Start condition hold time
t
HD:STA
0.6
-
-
4.0
-
-
Start condition setup time
t
SU:STA
0.6
-
-
4.7
-
-
Input data hold time
t
HD:DAT
0
-
-
0
-
-
Input data setup time
t
SU:DAT
100
-
-
250
-
-
Output data delay time
t
PD
0.1
-
0.9
0.2
-
3.5
Output data hold time
t
DH
0.1
-
-
0.2
-
-
Stop condition setup time
t
SU:STO
0.6
-
-
4.7
-
-
Bus release time before transfer start
tB
UF
1.2
-
-
4.7
-
-
Internal write cycle time
t
WR
-
-
5
-
-
5
Noise removal valid period (SDA, SCL terminal)
tI
-
-
0.1
-
-
0.1
WP hold time
t
HD:WP
0
-
-
0
-
-
WP setup time
t
SU:WP
0.1
-
-
0.1
-
-
WP valid time
t
HIGH:WP
1.0
-
-
1.0
-
-
*1 Not 100% tested
Unit
kHz
μs
μs
μs
μs
μs
μs
ns
ns
μs
μs
μs
μs
ms
μs
ns
μs
μs
●FAST-MODE
and STANDARD-MODE
FAST-MODE and STANDARD-MODE are of same operations, and mode is changed. They are distinguished by operating
speeds. 100kHz operation is called STANDARD-MODE, and 400kHz operation is called FAST-MODE. This operating
frequency is the maximum operating frequency, so 100kHz clock may be used in FAST-MODE. At V
CC
=2.5V to 5.5V,
400kHz, namely, operation is made in FASTMODE. (Operation is made also in STANDARD-MODE.)
●Sync
Data Input / Output Timing
tR
SCL
tF
tHIGH
SCL
tHD:STA
SDA
(入力)
(input)
tBUF
(output)
(出力)
tSU:DAT
tLOW
tHD:DAT
tSU:STA
tPD
tDH
tHD:STA
tSU:STO
SDA
SDA
START BIT
STOP BIT
○Input
read at the rise edge of SCL
○Data
output in sync with the fall of SCL
Figure 1-(a) Sync data input / output timing
SCL
Figure 1-(b) Start-stop bit timing
DATA(1)
SDA
D1
D0
ACK
DATA(n)
ACK
½WR
SCL
SDA
D0
Write data
ACK
½WR
Stop condition
Start condition
WP
Stop condition
ストップコンディション
(n-th
address)
tSU：WP
½HD：WP
Figure 1-(c) Write cycle timing
SCL
DATA(1)
SDA
D1
D0
ACK
tHIGH:WP
WP
DATA(n)
ACK
tWR
Figure 1-(d) WP timing at write execution
○At
write execution, in the area from the D0 taken clock rise of the first
DATA(1), to tWR, set WP=“LOW”.
○By
setting WP “HIGH” in the area, write can be cancelled.
When it is set WP=“HIGH” during tWR, write is forcibly ended, and data of
address under access is not guaranteed, therefore write it once again.
Figure 1-(e) WP timing at write cancel
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TSZ02201-0R1R0G100140-1-2
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BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)
●Block
Diagram
*2
A0
1
*1
1Kbit to 64Kbit EEPROM array
7bit 11bit
8bit 12bit
9bit 13b
it
10bi
t
8
8bit
Vcc
*2
A1
2
Address
decoder
*1
7bit 11bit
8bit 12bit
9bit 13b
it
10bi
t
Slave - word
address register
Data
register
7
WP
*2
START
STOP
A2
3
Control circuit
ACK
6
SCL
GND
4
High voltage
generating circuit
Power source
voltage detection
5
SDA
*1
7bit : BR24A01A-WM
8bit : BR24A02-WM
9bit : BR24A04-WM
10bit : BR24A08-WM
11bit : BR24A16-WM
12bit : BR24A32-WM
13bit : BR24A64-WM
*
2
A0=N.C.
A0, A1=N.C.
A0, A1= N.C. A2=Don’t Use
: BR24A04-WM
: BR24A08-WM
: BR24A16-WM
●Pin
Configuration
(TOP VIEW)
A0
1
BR24A01A-WM
BR24A02-WM
BR24A04-WM
BR24A08-WM
BR24A16-WM
BR24A32-WM
BR24A64-WM
8
Vcc
A1
2
7
WP
A2
3
6
SCL
GND
4
5
SDA
●Pin
Descriptions
Terminal
name
A0
A1
A2
GND
SDA
SCL
WP
Vcc
Input /
output
Input
Input
Input
-
Input /
output
Input
Input
-
Function
BR24A01A-WM BR24A02-WM BR24A04-WM BR24A08-WM BR24A16-WM BR24A32-WM BR24A64-WM
Slave address setting
Slave address setting
Slave address setting
Not connected
Not connected
Not used
Slave address setting
Slave address setting
Slave address setting
Reference voltage of all input / output, 0V
Slave and word address, Serial data input serial data output
Serial clock input
Write protect terminal
Connect the power source.
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© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
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TSZ02201-0R1R0G100140-1-2
29.Jan.2018 Rev.003
BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)
●Typical
Performance Curves
(The following values are Typ. ones.)
6
5
4
6
5
4
SPEC
3
2
1
SPEC
0
0
1
2
3
Vcc[V]
Figure 2. H input voltage VIH1,2
(SCL,SDA,WP)
4
5
6
0
1
2
3
4
5
6
Ta=105℃
Ta=-40℃
Ta=25℃
VIH[V]
2
1
0
Ta=105℃
Ta=-40℃
Ta=25℃
VIL[V]
3
Vcc[V]
Figure 3. L input voltageVIL1,2
(SCL,SDA,WP)
1
1.2
1.0
0.8
0.6
0.4
0.2
Ta=-40℃
0
0
1
2
3
IOL1[mA]
4
5
6
0
1
2
3
Vcc[V]
4
5
6
Ta=105℃
Ta=25℃
Ta=-40℃
SPEC
EC
0.8
0.6
VOL1[V]
SPEC Ta=105℃
0.4
Ta=25℃
0.2
0
Figure 4. L output voltage VOL1-IOL1
(V
CC
=2.5V)
ILI[μA]
Figure 5. Input leak current ILI
(SCL,WP)
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© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
5/28
TSZ02201-0R1R0G100140-1-2
29.Jan.2018 Rev.003
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