622.08 MHz) or Ethernet clock rates (e.g., 25 MHz,
50 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for
synchronizing Gigabit Ethernet PHYs
Programmable output synthesizer generates
telecom clock frequencies from any multiple of
8 kHz up to 100 MHz
Generates several styles of telecom frame pulses
with selectable pulse width, polarity and frequency
Internal state machine automatically controls mode
of operation (free-run, locked, holdover)
•
July 2009
Ordering Information
ZL30142GGG
64 Pin CABGA
Trays
ZL30142GGG2 64 Pin CABGA*
Trays
*Pb Free Tin/Silver/Copper
-40
o
C to +85
o
C
Flexible input reference monitoring automatically
disqualifies references based on frequency and
phase irregularities
Provides automatic reference switching and
holdover during loss of reference input
Supports master/slave configuration and dynamic
input to output delay compensation for
AdvancedTCA
TM
Configurable input to output delay and output to
output phase alignment
•
•
•
•
•
•
•
•
Applications
•
•
ITU-T G.8262 System Timing Cards which support
1 GbE interfaces
Telcordia GR-253 Carrier Grade SONET/SDH
Stratum 3 System Timing Cards
•
•
•
osci
ref0
ref1
ref2
/N1
/N2
ref
osco
SONET/
Ethernet
APLL
diff
apll_clk
DPLL
sync0
sync1
sync2
sync
Programmable
Synthesizer
N*8kHz
p_clk
p_fp
mode
lock
hold
I
2
C/SPI
JTAG
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2009, Zarlink Semiconductor Inc. All Rights Reserved.
ZL30142
1.0
High Level Overview
Short Form Data Sheet
The ZL30142 SONET/SDH/GbE Stratum 3 System Synchronizer and SETS device is a highly integrated device
that provides all of the functionality that is required for a central timing card in carrier grade network equipment. The
basic functions of a central timing card include:
•
•
•
•
•
•
•
Input reference monitoring for both frequency accuracy and phase irregularities
Automatic input reference selection
Support of both external timing and line timing modes
Hitless reference switching
Wander and jitter filtering
Master/slave crossover for minimizing phase alignment between redundant timing cards
Independent derived output timing path for support of the SETS functionality
In a typical application, the main timing path uses the DPLL to synchronize to either an external BITS source or to a
recovered line timed source. The DPLL monitors the references and automatically selects the best available
reference based on configurable priority and revertive properties. the DPLL provides the wander filtering function
and the P0 synthesizer generates a jitter filtered clock and frame pulse for the system timing bus which supplies all
line cards with a common timing reference.
B IT S A
B IT S B
C e n tra l
T im in g
C a rd
S
P
P
S
C e n tra l
T im in g
C a rd
ZL30142
XOVER
DPLL
DPLL
ZL30142
P
S
1 9 .4 4 M H z
1 9 .4 4 M H z
S
P
L in e R e c o v e r e d T im in g
P
A
S y s t e m T im in g B u s
1 9 .4 4 M H z
A
B
B
A
1 9 .4 4 M H z
B
S
T e le c o m
B a c k p la n e
P ro g
S y n th
ZL30146
Tx
DPLL
Tx
DPLL
ZL30146
P ro g
S y n th
Rx
DPLL
Rx
DPLL
APLL
8 kHz
PHY
O C -1 9 2
L in e C a r d
6 2 2 .0 8 M H z
APLL
1 5 6 .2 5 M H z
PHY
25 M Hz
10G bE
L in e C a r d
Figure 2 - Typical Application of the ZL30142
2
Zarlink Semiconductor Inc.
c Zarlink Semiconductor 2005 All rights reserved.
Package Code
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ACN
DATE
APPRD.
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