Data Sheet
FEATURES
14-Bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS
JESD204B, Dual Analog-to-Digital Converter
AD9680
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD
SPIVDD
(1.25V)
(1.25V) (2.5V) (3.3V)
(1.25V) (1.25V) (1.8V TO 3.3V)
BUFFER
DDC
JESD204B
HIGH SPEED SERIALIZER
JESD204B (Subclass 1) coded serial digital outputs
1.65 W total power per channel at 1 GSPS (default settings)
SFDR at 1 GSPS = 85 dBFS at 340 MHz, 80 dBFS at 1 GHz
SNR at 1 GSPS = 65.3 dBFS at 340 MHz (A
IN
= −1.0 dBFS),
60.5 dBFS at 1 GHz (A
IN
= −1.0 dBFS)
ENOB = 10.8 bits at 10 MHz
DNL = ±0.5 LSB
INL = ±2.5 LSB
Noise density = −154 dBFS/Hz at 1 GSPS
1.25 V, 2.5 V, and 3.3 V dc supply operation
No missing codes
Internal ADC voltage reference
Flexible input range: 1.46 V p-p to 1.94 V p-p
AD9680-1250: 1.58 V p-p nominal
AD9680-1000 and AD9680-820: 1.70 V p-p nominal
AD9680-500: 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal)
Programmable termination impedance
400 Ω, 200 Ω, 100 Ω, and 50 Ω differential
2 GHz usable analog input full power bandwidth
95 dB channel isolation/crosstalk
Amplitude detect bits for efficient AGC implementation
2 integrated wideband digital processors per channel
12-bit NCO, up to 4 half-band filters
Differential clock input
Integer clock divide by 1, 2, 4, or 8
Flexible JESD204B lane configurations
Small signal dither
VIN+A
VIN–A
ADC
CORE
14
Tx OUTPUTS
FAST
DETECT
FD_A
SIGNAL
MONITOR
4
FD_B
VIN+B
VIN–B
SERDOUT0±
SERDOUT1±
SERDOUT2±
SERDOUT3±
14
ADC
CORE
BUFFER
DDC
V_1P0
CONTROL
REGISTERS
FAST
DETECT
JESD204B
SUBCLASS 1
CONTROL
SYNCINB±
SYSREF±
CLOCK
GENERATION
CLK+
CLK–
SIGNAL
MONITOR
÷2
÷4
÷8
AGND
DRGND DGND
SPI CONTROL
AD9680
SDIO SCLK CSB
PDWN/
STBY
11752-001
Figure 1.
PRODUCT HIGHLIGHTS
1.
2.
3.
Wide full power bandwidth supports IF sampling of signals
up to 2 GHz.
Buffered inputs with programmable input termination eases
filter design and implementation.
Four integrated wideband decimation filters and numerically
controlled oscillator (NCO) blocks supporting multiband
receivers.
Flexible serial port interface (SPI) controls various product
features and functions to meet specific system requirements.
Programmable fast overrange detection.
9 mm × 9 mm, 64-lead LFCSP.
APPLICATIONS
Communications
Diversity multiband, multimode digital receivers
3G/4G, TD-SCDMA, W-CDMA, GSM, LTE
General-purpose software radios
Ultrawideband satellite receivers
Instrumentation
Radars
Signals intelligence (SIGINT)
DOCSIS 3.0 CMTS upstream receive paths
HFC digital reverse path receivers
4.
5.
6.
Rev. D
Document Feedback
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license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
AD9680
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 3
General Description ......................................................................... 5
Specifications..................................................................................... 6
DC Specifications ......................................................................... 6
AC Specifications.......................................................................... 7
Digital Specifications ................................................................... 9
Switching Specifications ............................................................ 10
Timing Specifications ................................................................ 11
Absolute Maximum Ratings.......................................................... 13
Thermal Characteristics ............................................................ 13
ESD Caution ................................................................................ 13
Pin Configuration and Function Descriptions ........................... 14
Typical Performance Characteristics ........................................... 16
AD9680-1250 .............................................................................. 16
AD9680-1000 .............................................................................. 20
AD9680-820 ................................................................................ 25
AD9680-500 ................................................................................ 30
Equivalent Circuits ......................................................................... 34
Theory of Operation ...................................................................... 36
ADC Architecture ...................................................................... 36
Analog Input Considerations.................................................... 36
Voltage Reference ....................................................................... 42
Clock Input Considerations ...................................................... 43
ADC Overrange and Fast Detect.................................................. 45
ADC Overrange .......................................................................... 45
Fast Threshold Detection (FD_A and FD_B) ........................ 45
Signal Monitor ................................................................................ 46
SPORT Over JESD204B ............................................................. 47
Digital Downconverter (DDC) ..................................................... 49
DDC I/Q Input Selection .......................................................... 49
DDC I/Q Output Selection ....................................................... 49
DDC General Description ........................................................ 49
Frequency Translation ................................................................... 55
Frequency Translation General Description .............................. 55
DDC NCO Plus Mixer Loss and SFDR ................................... 56
Numerically Controlled Oscillator........................................... 56
FIR Filters ........................................................................................ 58
Rev. D | Page 2 of 103
Data Sheet
FIR Filters General Description ............................................... 58
Half-Band Filters ........................................................................ 59
DDC Gain Stage ......................................................................... 61
DDC Complex to Real Conversion ......................................... 61
DDC Example Configurations ................................................. 62
Digital Outputs ............................................................................... 65
Introduction to the JESD204B Interface ................................. 65
JESD204B Overview .................................................................. 65
Functional Overview ................................................................. 66
JESD204B Link Establishment ................................................. 66
Physical Layer (Driver) Outputs .............................................. 68
JESD204B Tx Converter Mapping ........................................... 70
Configuring the JESD204B Link .............................................. 72
Deterministic Latency.................................................................... 75
Subclass 0 Operation.................................................................. 75
Subclass 1 Operation.................................................................. 75
Multichip Synchronization............................................................ 77
Normal Mode.............................................................................. 77
Timestamp Mode ....................................................................... 77
SYSREF± Input ........................................................................... 79
SYSREF± Setup/Hold Window Monitor ................................. 81
Latency ............................................................................................. 83
End to End Total Latency .......................................................... 83
Example Latency Calculation ................................................... 83
Test Modes ....................................................................................... 84
ADC Test Modes ........................................................................ 84
JESD204B Block Test Modes .................................................... 85
Serial Port Interface ........................................................................ 87
Configuration Using the SPI ..................................................... 87
Hardware Interface..................................................................... 87
SPI Accessible Features .............................................................. 87
Memory Map .................................................................................. 88
Reading the Memory Map Register Table............................... 88
Memory Map Register Table ..................................................... 89
Applications Information ............................................................ 102
Power Supply Recommendations........................................... 102
Exposed Pad Thermal Heat Slug Recommendations .......... 102
AVDD1_SR (Pin 57) and AGND (Pin 56 and Pin 60) ............ 102
Outline Dimensions ..................................................................... 103
Ordering Guide ........................................................................ 103
Data Sheet
REVISION HISTORY
11/2017—Rev. C to Rev. D
Changes to Table 2 ............................................................................ 7
Change to Junction Temperature Range, Table 6........................13
Changes to Figure 17 ......................................................................17
Changes to Figure 18 ......................................................................18
Changes to Figure 34 ......................................................................20
Changes to Figure 65 and Figure 66 .............................................26
Changes to Figure 67 and Figure 68 .............................................27
Changes to Figure 118 to Figure 120 ............................................38
Added Deterministic Latency Section, Subclass 0 Operation
Section, Subclass 1 Operation Section, Deterministic Latency
Requirements Section, Setting Deterministic Latency Registers
Section, and Figure 171; Renumbered Sequentially ...................75
Added Figure 172 and Figure 173 .................................................76
Changes to Multichip Synchronization Section ..........................77
Added Normal Mode Section, Timestamp Mode Section, and
Figure 174 .........................................................................................77
Added Figure 175 ............................................................................78
Added SYSREF± Input Section, SYSREF± Control Features
Section, and Figure 176 to Figure 179 ..........................................79
Added Figure 180 and Figure 181 .................................................80
Added Latency Section, End to End Total Latency Section,
Example Latency Calculation Section, and Table 29 to
Table 31 .............................................................................................83
Updated Outline Dimensions ......................................................103
Changes to Ordering Guide .........................................................103
11/2015—Rev. B to Rev. C
Added AD9680-1250 ......................................................... Universal
Changes to Features Section ............................................................ 1
Change to General Description Section ......................................... 4
Changes to Table 1 ............................................................................ 5
Changes to Table 2 ............................................................................ 6
Changes to Table 4 ............................................................................ 9
Changes to Table 5 ..........................................................................10
Changes to Figure 4.........................................................................11
Changes to Pin 14 Description, Table 8 .......................................14
Added AD9680-1250 Section and Figure 6 to Figure 29;
Renumbered Sequentially ..............................................................15
Changes to Figure 113 ....................................................................34
Changes to Analog Input Considerations Section ......................35
Changes to Table 9 ..........................................................................36
Changes to Input Buffer Control Registers (0x018, 0x019,
0x01A, 0x935, 0x934, 0x11A) Section ..........................................37
Added Figure 118 to Figure 120 ....................................................37
Changes to Table 10 ........................................................................40
Changes to Table 17 ........................................................................57
Changes to ADC Test Modes Section...........................................78
Changes to Table 36 ........................................................................83
Changes to Ordering Guide ...........................................................97
3/2015—Rev. A to Rev. B
Added AD9680-820 ........................................................... Universal
AD9680
Changes to Features Section ............................................................ 1
Changes to Table 1 ............................................................................ 5
Changes to Table 2 ............................................................................ 6
Changes to Table 3 ............................................................................ 8
Changes to Table 4 ............................................................................ 9
Added Figure 14; Renumbered Sequentially ............................... 15
Added AD9680-820 Section and Figure 31 Through Figure 36 ... 19
Added Figure 37 Through Figure 42 ............................................ 20
Added Figure 43 Through Figure 48 ............................................ 21
Added Figure 49 Through Figure 54 ............................................ 22
Added Figure 55 .............................................................................. 23
Changes to Figure 69 and Figure 70 ............................................. 26
Changes to Input Buffer Control Registers (0x018, 0x019, 0x01A,
0x935, 0x934, 0x11A) Section, Table 9, and Figure 93.................... 31
Added Figure 99 Through Figure 100 .......................................... 33
Changes to Table 10 ........................................................................ 34
Changes to Clock Jitter Considerations Section ......................... 37
Added Figure 112 ............................................................................ 37
Changes to Digital Downconverter (DDC) Section................... 42
Changes to Table 17 ........................................................................ 51
Changes to Table 36 ........................................................................ 77
Changes to Ordering Guide ........................................................... 91
12/2014—Rev. 0 to Rev. A
Added AD9680-500 ........................................................... Universal
Changes to Features Section and Figure 1 ..................................... 1
Changes to General Description Section ....................................... 4
Changes to Specifications Section and Table 1 ............................. 5
Changes to AC Specifications Section and Table 2....................... 6
Changes to Digital Specifications Section ..................................... 8
Changes to Switching Specifications Section and Table 4 ........... 9
Changes to Table 6, Thermal Characteristics Section, and
Table 7 ............................................................................................... 11
Change to Digital Inputs Description, Table 8 ............................ 13
Added AD9680-1000 Section, Figure 10, and Figure 11;
Renumbered Sequentially .............................................................. 14
Changes to Figure 6 to Figure 9 .................................................... 14
Added Figure 12 to Figure 14 ........................................................ 15
Changes to Figure 15 to Figure 17 ................................................ 15
Changes to Figure 18 to Figure 21 ................................................ 16
Changes to Figure 25 and Figure 29 ............................................. 17
Changes to Figure 30 ...................................................................... 18
Deleted Figure 35, Figure 36, and Figure 38 ................................ 19
Added AD9680-500 Section and Figure 31 to Figure 54 ............. 19
Changes to Analog Input Considerations Section and
Differential Input Configurations Section ................................... 25
Added Input Buffer Control Registers (0x018, 0x019, 0x01A,
0x935, 0x934, 0x11A) Section, Figure 66, Figure 68, and Table 9;
Renumbered Sequentially .............................................................. 26
Changes to Analog Input Buffer Controls and SFDR
Optimization Section and Figure 67 ............................................ 26
Added Figure 69 to Figure 72 ........................................................ 27
Added Figure 73 to Figure 75 ........................................................ 28
Rev. D | Page 3 of 103
AD9680
Changes to Table 10 ........................................................................ 28
Added Input Clock Divider ½ Period Delay Adjust Section and
Clock Fine Delay Adjust Section .................................................. 30
Changes to Figure 83 and Temperature Diode Section ............. 31
Added Signal Monitor Section and Figure 86 to Figure 89 ...... 33
Changes to Table 11 ........................................................................ 39
Changes to Table 12 to Table 14 ................................................... 40
Changes to Table 16 ........................................................................ 41
Deleted Figure 65 and Figure 66 ................................................... 45
Changes to Table 17 ........................................................................ 45
Changes to Table 19 to Table 20 ................................................... 46
Changes to Table 22 ........................................................................ 47
Changes to Table 23 ........................................................................ 49
Changes to JESD204B Link Establishment Section ................... 53
Data Sheet
Added Figure 105 to Figure 110 ................................................... 56
Changes to Example 1: Full Bandwidth Mode Section ............. 60
Added Multichip Synchronization Section, Figure 115 to
Figure 117, and Table 28 ................................................................ 62
Added Test Modes Section and Table 29 to Table 33................. 66
Changes to Reading the Memory Map Register Table Section .......70
Changes to Table 36 ....................................................................... 71
Changes to Power Supply Recommendations Section,
Figure 118, and Exposed Pad Thermal Heat Slug
Recommendations Section ............................................................ 83
Changes to Ordering Guide .......................................................... 84
5/2014—Revision 0: Initial Version
Rev. D | Page 4 of 103
Data Sheet
GENERAL DESCRIPTION
The AD9680 is a dual, 14-bit, 1.25 GSPS/1 GSPS/820 MSPS/
500 MSPS analog-to-digital converter (ADC). The device has
an on-chip buffer and sample-and-hold circuit designed for low
power, small size, and ease of use. This device is designed for
sampling wide bandwidth analog signals of up to 2 GHz. The
AD9680 is optimized for wide input bandwidth, high sampling
rate, excellent linearity, and low power in a small package.
The dual ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations.
The analog input and clock signals are differential inputs. Each
ADC data output is internally connected to two digital down-
converters (DDCs). Each DDC consists of up to five cascaded
signal processing stages: a 12-bit frequency translator (NCO),
and four half-band decimation filters. The DDCs are bypassed
by default.
In addition to the DDC blocks, the AD9680 has several
functions that simplify the automatic gain control (AGC)
AD9680
function in the communications receiver. The programmable
threshold detector allows monitoring of the incoming signal
power using the fast detect output bits of the ADC. If the input
signal level exceeds the programmable threshold, the fast detect
indicator goes high. Because this threshold indicator has low
latency, the user can quickly turn down the system gain to avoid
an overrange condition at the ADC input.
Users can configure the Subclass 1 JESD204B-based high speed
serialized output in a variety of one-, two-, or four-lane
configurations, depending on the DDC configuration and the
acceptable lane rate of the receiving logic device. Multiple device
synchronization is supported through the SYSREF± and
SYNCINB± input pins.
The AD9680 has flexible power-down options that allow
significant power savings when desired. All of these features can
be programmed using a 1.8 V to 3.3 V capable, 3-wire SPI.
The AD9680 is available in a Pb-free, 64-lead LFCSP and is
specified over the −40°C to +85°C industrial temperature range.
This product is protected by a U.S. patent.
Rev. D | Page 5 of 103
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