5962F1120202QXA datasheet, PDF

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5962F1120202QXA: DescriptionQDR SRAM, 2MX36, 0.85ns, CMOS, CBGA165, CGA-165; Categorystorage storage; File Size433KB，34 Pages; ManufacturerCypress Semiconductor

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5962F1120202QXA Overview

QDR SRAM, 2MX36, 0.85ns, CMOS, CBGA165, CGA-165

5962F1120202QXA Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Cypress Semiconductor
package instruction	CGA-165
Reach Compliance Code	compli
ECCN code	3A991.B.2.A
Maximum access time	0.7 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	250 MHz
I/O type	SEPARATE
JESD-30 code	R-CBGA-X165
length	25 mm
memory density	75497472 bi
Memory IC Type	QDR SRAM
memory width	36
Number of functions	1
Number of terminals	165
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	2MX36
Output characteristics	3-STATE
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	CGA
Encapsulate equivalent code	CGA165,11X15,50
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
power supply	1.8 V
Certification status	Qualified
Filter level	MIL-STD-883
Maximum seat height	5.38 mm
Maximum standby current	0.57 A
Maximum slew rate	1.275 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	UNSPECIFIED
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	21 mm

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CYRS1543AV18

CYRS1545AV18

72-Mbit QDR

II+ SRAM Four-Word

Burst Architecture with RadStop™ Technology

72-Mbit QDR

II+ SRAM Four-Word Burst Architecture with RadStop™ Technology

Radiation Performance

Radiation Data

■

HSTL inputs and variable drive HSTL output buffers

JTAG 1149.1 compatible test access port

DLL for accurate data placement

Total Dose

=300

Krad

Soft error rate (both

Heavy Ion

and proton)

Heavy ions



1 × 10

-10

upsets/bit-day with an external SECDED

EDAC Controller

Neutrons

= 2.0 × 10

N/cm

Dose rate = 2.0 × 10

rad(Si)/sec

Dose rate survivability (rad(Si)/sec) = 1.5 × 10^11 (rad(Si)/sec

Latch up immunity = 120 MeV.cm

/mg (125 °C)

Configurations

CYRS1543AV18 – 4 M × 18

CYRS1545AV18 – 2 M × 36

■

Functional Description

The CYRS1543AV18 and CYRS1545AV18 are synchronous

pipelined SRAMs, equipped with 1.8 V QDR II+ architecture with

RadStop™ technology. Cypress’s state-of-the-art

RadStop

Technology

is radiation hardened through proprietary design and

process hardening techniques.

The QDR II+ architecture consists of two separate ports: the read

port and the write port to access the memory array. The read port

has dedicated data outputs to support read operations and the

write port has dedicated data inputs to support write operations.

QDR II+ architecture has separate data inputs and data outputs

to completely eliminate the need to turnaround the data bus that

exists with common I/O devices. Each port can be accessed

through a common address bus. Addresses for read and write

addresses are latched on alternate rising edges of the input (K)

clock. Accesses to the QDR II+ read and write ports are

completely independent of one another. To maximize data

throughput, both read and write ports are equipped with DDR

interfaces. Each address location is associated with four 18-bit

words (CYRS1543AV18) or 36-bit words (CYRS1545AV18) that

burst sequentially into or out of the device. Because data can be

transferred into and out of the device on every rising edge of both

input clocks (K and K), memory bandwidth is maximized while

simplifying system design by eliminating bus turnarounds.

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

For a complete list of related resources,

click here.

Prototyping

■

Non-qualified CYPT1543AV18, and CYPT1545AV18 devices

with same functional and timing characteristics in a

165-ball Ceramic Column Grid Array

(CCGA) package

Features

■

Separate independent read and write data ports

❐

Supports concurrent transactions

250 MHz clock for high bandwidth

Four-word burst for reducing address bus frequency

Double data rate (DDR) interfaces on both read and write ports

at 250 MHz (data transferred at 500 MHz)

Two input clocks (K and K) for precise DDR timing

❐

SRAM uses rising edges only

Echo clocks (CQ and CQ) simplify data capture in high speed

systems

Single multiplexed address input bus latches address inputs

for read and write ports

Separate port selects for depth expansion

Synchronous internally self-timed writes

QDR

II+ operates with 2.0 cycle read latency when the delay

lock loop (DLL) is enabled

Available in × 18, and × 36 configurations

Full data coherency, providing most current data

Core V

= 1.8 (± 0.1 V); I/O V

DDQ

= 1.4 V to V

Available in 165-ball CCGA (21 × 25 × 2.83 mm)

■

Selection Guide

Description

Maximum operating frequency

Maximum operating current (125 °C,

concurrent R/W)

× 18

× 36

250 MHz

250

1275

Unit

MHz

Cypress Semiconductor Corporation

Document Number: 001-60007 Rev. *L

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised January 9, 2015

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