CYRS1049DV33
4-Mbit (512 K × 8) Static RAM
with RadStop™ Technology
4-Mbit (512 K × 8) Static RAM with RadStop™ Technology
Radiation Performance
Radiation Data
■
■
Features
■
Total dose =300
Krad
Soft error rate (both heavy ion and proton)
Heavy ions
1 × 10
-10
upsets/bit-day with single-error
correction, double error detection error detection and
correction (SEC-DED EDAC)
Neutron
= 2.0 × 10
14
N/cm
2
Dose rate > 2.0 × 10 (rad(Si)/s)
Latch up immunity
LET
= 120 MeV.cm
2
/mg (125
C)
■
■
■
■
■
■
Temperature ranges
❐
Military/Space: –55 °C to 125 °C
High speed
❐
t
AA
= 12 ns
Low active power
❐
I
CC
= 95 mA at 12 ns (P
MAX
= 315 mW)
Low CMOS standby power
❐
I
SB2
= 15 mA
2.0 V data retention
Automatic power-down when deselected
Transistor-transistor logic (TTL) compatible inputs and outputs
Easy memory expansion with CE and OE features
Available in Pb-free 36-pin ceramic flat package
■
■
■
■
■
9
Processing Flows
■
■
Q Grade - Class Q flow in compliance with MIL-PRF 38535
V Grade - Class V flow in compliance with MIL-PRF 38535
Prototyping Options
■
■
CYPT1049DV33 protos with same functional and timing as
flight units using non-radiation hardened die
Characteristics in a 36-pin ceramic flat package
For a complete list of related documentation,
click here.
Logic Block Diagram
INPUT BUFFER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
CE
WE
OE
I/O
IO0
0
IO1
1
I/O
ROW DECODER
SENSE AMPS
IO2
I/O
2
512K x 8
ARRAY
I/O
IO3
3
I/O
IO4
4
I/O
IO5
5
I/O
IO6
6
COLUMN DECODER
POWER
DOWN
IO7
7
I/O
A11
A12
A13
A14
A15
A16
A17
A18
Cypress Semiconductor Corporation
Document Number: 001-64292 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 17, 2014
CYRS1049DV33
Contents
Functional Description ..................................................... 3
Selection Guide ................................................................ 3
Pin Configuration ............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
DC Electrical Characteristics .......................................... 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
AC Switching Characteristics ......................................... 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagram ............................................................ 13
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Glossary .......................................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC® Solutions ...................................................... 16
Cypress Developer Community ................................. 16
Technical Support ..................................................... 16
Document Number: 001-64292 Rev. *F
Page 2 of 16
CYRS1049DV33
Functional Description
The CYRS1049DV33 is a high-performance complementary
metal oxide semiconductor (CMOS) static RAM organized as
512 K words by 8 bits with RadStop™ technology. Cypress’s
state-of-the-art RadStop technology is radiation hardened
through proprietary design and process hardening techniques.
The 4-Mbit fast asynchronous SRAM with RadStop technology
is also QML V certified with Defense Logistics Agency Land and
Maritime (DLAM).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the eight I/O pins (I/O
0
through I/O
7
)
is then written into the location specified on the address pins (A
0
through A
18
).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins appear on the I/O pins. See the
Truth Table on page 11
for a complete description of read and
write modes.
The eight input or output pins (I/O
0
through I/O
7
) are placed in a
high impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), or during a write operation
(CE LOW, and WE LOW)
The CYRS1049DV33 is available in a ceramic 36-pin Flat
package with center power and ground (revolutionary) pinout.
Easy memory expansion is provided by utilizing OE, CE, and
tri-state drivers.
For best practice recommendations, refer to the Cypress
application note
AN1064, SRAM System Guidelines.
Selection Guide
Description
Maximum access time
Maximum operating current
Maximum CMOS standby current
Military/Space
12
95
15
Unit
ns
mA
mA
Pin Configuration
Figure 1. 36-pin Ceramic Flat Package pinout (Top View)
[1]
A
0
A
1
A
2
A
3
A
4
CE
IO
0
IO
1
V
CC
GND
IO
2
IO
3
WE
A
5
A
6
A
7
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A
18
A
17
A
16
A
15
OE
IO
7
IO
6
GND
V
CC
IO
5
IO
4
A
14
A
13
A
12
A
11
A
10
DNU
Note
1. NC pins are not connected on the die.
Document Number: 001-64292 Rev. *F
Page 3 of 16
CYRS1049DV33
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65
C
to +150
C
Ambient temperature with
power applied .......................................... –55
C
to +125
C
Supply voltage on
V
CC
relative to GND
[2]
................................–0.3 V to +4.6 V
DC voltage applied to outputs
in High Z state
[2]
................................ –0.5 V to V
CC
+ 0.5 V
DC input voltage
[2]
............................. –0.5 V to V
CC
+ 0.5 V
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. > 2001 V
Latch up current ..................................................... > 140 mA
Operating Range
Range
Military/Space
Ambient
Temperature
V
CC
Speed
12 ns
–55
C
to +125
C
3.3 V
0.3 V
DC Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH [2]
V
IL [2]
I
IX
I
OZ
I
CC
Description
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input leakage current
Output leakage current
V
CC
operating supply current
GND < V
I
< V
CC
GND < V
OUT
< V
CC
, output disabled
V
CC
= Max, f = f
MAX
= 1/t
RC
83 MHz
66 MHz
40 MHz
I
SB1
I
SB2
Automatic CE power-down
current – TTL inputs
Automatic CE power-down
current – CMOS inputs
Max V
CC
, CE > V
IH
V
IN
> V
IH
or V
IN
< V
IL
, f = f
MAX
Max V
CC
, CE > V
CC
– 0.3 V,
V
IN
> V
CC
– 0.3 V, or V
IN
< 0.3 V, f = 0
Test Conditions
V
CC
= Min, I
OH
= –4.0 mA
V
CC
= Min, I
OL
= 8.0 mA
Military/Space
Min
2.4
–
2.0
–0.3
–1
–1
–
–
–
–
–
Max
–
0.4
V
CC
+ 0.3
0.8
+1
+1
95
85
75
15
15
Unit
V
V
V
V
A
A
mA
mA
mA
mA
mA
Note
2. V
IL(min)
= –2.0 V and V
IH(max)
= V
CC
+ 2 V for pulse durations of less than 20 ns.
Document Number: 001-64292 Rev. *F
Page 4 of 16
CYRS1049DV33
Capacitance
Parameter
[3]
C
IN
C
OUT
Description
Input capacitance
I/O capacitance
Test Conditions
T
A
= 25
C,
f = 1 MHz, V
CC
= 3.3 V
Max
8
8
Unit
pF
pF
Thermal Resistance
Parameter
[3]
JC
Description
Thermal resistance
(junction to case)
Test Conditions
Test according to MIL-PRF 38538
Ceramic Flat
Package
3.6
Unit
C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
[4]
Z = 50
Output
50
* Capacitive load consists
of all components of the
test environment
High-Z Characteristics
3.3 V
OUTPUT
5 pF
R2
351
(c)
R 317
1.5 V
Rise Time: 1 V/ns
(a)
Fall Time: 1 V/ns
30 pF*
All Input Pulses
90%
10%
90%
10%
3.0 V
GND
(b)
Notes
3. Tested initially and after any design or process changes that may affect these parameters.
4. AC characteristics (except High Z) are tested using the load conditions shown in
Figure 2
(a). High Z characteristics are tested for all speeds using the test load shown
in
Figure 2
(c).
Document Number: 001-64292 Rev. *F
Page 5 of 16
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