CY7C1263XV18
CY7C1265XV18
36-Mbit QDR
®
II+ Xtreme SRAM Four-Word
Burst Architecture (2.5 Cycle Read Latency)
36-Mbit QDR
®
II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
Features
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Configurations
With Read Cycle Latency of 2.5 cycles:
CY7C1263XV18 – 2 M × 18
CY7C1265XV18 – 1 M × 36
Separate Independent Read and Write Data Ports
❐
Supports concurrent transactions
633 MHz Clock for High Bandwidth
Four-word Burst for Reducing Address Bus Frequency
Double Data Rate (DDR) Interfaces on both Read and Write
Ports (data transferred at 1266 MHz) at 633 MHz
Available in 2.5 Clock Cycle Latency
Two Input Clocks (K and K) for precise DDR Timing
❐
SRAM uses rising edges only
Echo Clocks (CQ and CQ) simplify Data Capture in High Speed
Systems
Data Valid Pin (QVLD) to indicate Valid Data on the Output
Single Multiplexed Address Input Bus latches Address Inputs
for Read and Write Ports
Separate Port selects for Depth Expansion
Synchronous Internally Self-timed Writes
QDR
®
II+ Xtreme operates with 2.5 cycle read latency when
DOFF is asserted HIGH
Operates similar to QDR I Device with one Cycle Read Latency
when DOFF is asserted LOW
Available in × 18 and × 36 Configurations
Full Data Coherency, providing Most Current Data
Core V
DD
= 1.8 V ± 0.1 V; I/O V
DDQ
= 1.4 V to 1.6 V
❐
Supports 1.5 V I/O supply
HSTL Inputs and Variable Drive HSTL Output Buffers
Available in 165-ball FBGA Package (13 × 15 × 1.4 mm)
Offered in Pb-free Packages
JTAG 1149.1 compatible Test Access Port
Phase-Locked Loop (PLL) for Accurate Data Placement
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Functional Description
The CY7C1263XV18, and CY7C1265XV18 are 1.8 V
Synchronous Pipelined SRAMs, equipped with QDR II+
architecture. Similar to QDR II architecture, QDR II+ architecture
consists of two separate ports: the read port and the write port to
access the memory array. The read port has dedicated data
outputs to support read operations and the write port has
dedicated data inputs to support write operations. QDR II+
architecture has separate data inputs and data outputs to
completely eliminate the need to “turnaround” the data bus that
exists with common I/O devices. Each port is accessed through
a common address bus. Addresses for read and write addresses
are latched on alternate rising edges of the input (K) clock.
Accesses to the QDR II+ Xtreme read and write ports are
completely independent of one another. To maximize data
throughput, both read and write ports are equipped with DDR
interfaces. Each address location is associated with four 18-bit
words (CY7C1263XV18), or 36-bit words (CY7C1265XV18) that
burst sequentially into or out of the device. Because data is
transferred into and out of the device on every rising edge of both
input clocks (K and K), memory bandwidth is maximized while
simplifying system design by eliminating bus “turnarounds”.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
For a complete list of related documentation, click
here.
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Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
× 18
× 36
633 MHz
633
1165
1660
600 MHz
600
1100
1570
Unit
MHz
mA
Cypress Semiconductor Corporation
Document Number: 001-70328 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised January 3, 2018
CY7C1263XV18
CY7C1265XV18
Logic Block Diagram – CY7C1263XV18
D
[17:0]
18
Read Add. Decode
Write Add. Decode
A
(18:0)
19
Write
Reg
Address
Register
Write
Reg
Write
Reg
Write
Reg
Address
Register
19
A
(18:0)
512K x 18 Array
512K x 18 Array
512K x 18 Array
512K x 18 Array
K
K
CLK
Gen.
Control
Logic
RPS
DOFF
Read Data Reg.
CQ
72
V
REF
WPS
BWS
[1:0]
36
Control
Logic
36
Reg.
Reg.
Reg. 18
18
18
18
CQ
18
Q
[17:0]
QVLD
Logic Block Diagram – CY7C1265XV18
D
[35:0]
36
Read Add. Decode
Write Add. Decode
A
(17:0)
18
Write
Reg
Address
Register
Write
Reg
Write
Reg
Write
Reg
Address
Register
18
A
(17:0)
256K x 36 Array
256K x 36 Array
256K x 36 Array
256K x 36 Array
K
K
CLK
Gen.
Control
Logic
RPS
DOFF
Read Data Reg.
CQ
144
V
REF
WPS
BWS
[3:0]
72
Control
Logic
72
Reg.
Reg.
Reg. 36
36
36
36
CQ
36
Q
[35:0]
QVLD
Document Number: 001-70328 Rev. *F
Page 2 of 30
CY7C1263XV18
CY7C1265XV18
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Read Operations ......................................................... 6
Write Operations ......................................................... 6
Byte Write Operations ................................................. 7
Concurrent Transactions ............................................. 7
Depth Expansion ......................................................... 7
Programmable Impedance .......................................... 7
Echo Clocks ................................................................ 7
Valid Data Indicator (QVLD) ........................................ 7
PLL .............................................................................. 7
Application Example ........................................................ 8
Truth Table ........................................................................ 9
Write Cycle Descriptions ............................................... 10
Write Cycle Descriptions ............................................... 11
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 12
Disabling the JTAG Feature ...................................... 12
Test Access Port ....................................................... 12
Performing a TAP Reset ........................................... 12
TAP Registers ........................................................... 12
TAP Instruction Set ................................................... 12
TAP Controller State Diagram ....................................... 14
TAP Controller Block Diagram ...................................... 15
TAP Electrical Characteristics ...................................... 15
TAP AC Switching Characteristics ............................... 16
TAP Timing and Test Conditions .................................. 17
Identification Register Definitions ................................ 18
Scan Register Sizes ....................................................... 18
Instruction Codes ........................................................... 18
Boundary Scan Order .................................................... 19
Power Up Sequence in QDR II+ Xtreme SRAM ............ 20
Power Up Sequence ................................................. 20
PLL Constraints ......................................................... 20
Maximum Ratings ........................................................... 21
Neutron Soft Error Immunity ......................................... 21
Operating Range ............................................................. 21
Electrical Characteristics ............................................... 21
DC Electrical Characteristics ..................................... 21
AC Electrical Characteristics ..................................... 22
Capacitance .................................................................... 22
Thermal Resistance ........................................................ 22
AC Test Loads and Waveforms ..................................... 23
Switching Characteristics .............................................. 24
Switching Waveforms .................................................... 25
Read/Write/Deselect Sequence ................................ 25
Ordering Information ...................................................... 26
Ordering Code Definitions ......................................... 26
Package Diagram ............................................................ 27
Acronyms ........................................................................ 28
Document Conventions ................................................. 28
Units of Measures ..................................................... 28
Document History Page ................................................. 29
Sales, Solutions, and Legal Information ...................... 30
Worldwide Sales and Design Support ....................... 30
Products .................................................................... 30
PSoC® Solutions ...................................................... 30
Cypress Developer Community ................................. 30
Technical Support ..................................................... 30
Document Number: 001-70328 Rev. *F
Page 3 of 30
CY7C1263XV18
CY7C1265XV18
Pin Configurations
The pin configurations for CY7C1263XV18, and CY7C1265XV18 follow.
[1]
Figure 1. 165-ball FBGA (13 × 15 × 1.4 mm) pinout
CY7C1263XV18 (2 M × 18)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/144M
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
3
A
D9
D10
Q10
Q11
D12
Q13
V
DDQ
D14
Q14
D15
D16
Q16
Q17
A
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
1
NC
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
QVLD
NC
7
NC/288M
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
RPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
NC/72M
NC
Q7
NC
D6
NC
NC
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
CY7C1265XV18 (1 M × 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
Q27
D27
D28
Q29
Q30
D30
DOFF
D31
Q32
Q33
D33
D34
Q35
TDO
2
Q18
Q28
D20
D29
Q21
D22
V
REF
Q31
D32
Q24
Q34
D26
D35
TCK
3
D18
D19
Q19
Q20
D21
Q22
V
DDQ
D23
Q23
D24
D25
Q25
Q26
A
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
2
BWS
3
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
QVLD
NC
7
BWS
1
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
RPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
D17
D16
Q16
Q15
D14
Q13
V
DDQ
D12
Q12
D11
D10
Q10
Q9
A
10
NC/144M
Q17
Q7
D15
D6
Q14
D13
V
REF
Q4
D3
Q11
Q1
D9
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
NC/288M NC/72M
Note
1. NC/72M, NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-70328 Rev. *F
Page 4 of 30
CY7C1263XV18
CY7C1265XV18
Pin Definitions
Pin Name
D
[x:0]
I/O
Pin Description
Input-
Data Input Signals.
Sampled on the rising edge of K and K clocks when valid write operations are active.
Synchronous CY7C1263XV18
D
[17:0]
CY7C1265XV18
D
[35:0]
Input-
Write Port Select
Active LOW.
Sampled on the rising edge of the K clock. When asserted active, a
Synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D
[x:0]
.
Input-
Byte Write Select 0, 1, 2 and 3
Active LOW.
Sampled on the rising edge of the K and K clocks when
Synchronous write operations are active. Used to select which byte is written into the device during the current portion
of the write operations. Bytes not written remain unaltered.
CY7C1263XV18
BWS
0
controls D
[8:0]
and BWS
1
controls D
[17:9].
CY7C1265XV18
BWS
0
controls D
[8:0]
, BWS
1
controls D
[17:9]
, BWS
2
controls D
[26:18]
and BWS
3
controls
D
[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
Input-
Address Inputs.
Sampled on the rising edge of the K clock during active read and write operations. These
Synchronous address inputs are multiplexed for both read and write operations. Internally, the device is organized as
2 M × 18 (4 arrays each of 512 K × 18) for CY7C1263XV18 and 1 M × 36 (4 arrays each of 256 K × 36)
for CY7C1265XV18. Therefore, only 19 address inputs are needed to access the entire memory array for
CY7C1263XV18 and 18 address inputs for CY7C1265XV18. These inputs are ignored when the
appropriate port is deselected. The address pins (A) can be assigned any bit order.
Outputs-
Data Output Signals.
These pins drive out the requested data when the read operation is active. Valid
Synchronous data is driven out on the rising edge of the K and K clocks during read operations. On deselecting the
read port, Q
[x:0]
are automatically tristated.
CY7C1263XV18
Q
[17:0]
CY7C1265XV18
Q
[35:0]
Input-
Read Port Select
Active LOW.
Sampled on the rising edge of positive input clock (K). When active, a
Synchronous read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is
allowed to complete and the output drivers are automatically tristated following the next rising edge of the
K clock. Each read access consists of a burst of four sequential transfers.
Valid output
Valid Output Indicator.
The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ.
indicator
Input Clock
Input Clock
Echo Clock
Positive Input Clock Input.
The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q
[x:0]
. All accesses are initiated on the rising edge of K.
Negative Input Clock Input.
K is used to capture synchronous inputs being presented to the device and
to drive out data through Q
[x:0]
.
Synchronous Echo Clock Outputs.
This is a free running clock and is synchronized to the input clock
(K) of the QDR II+ Xtreme. The timings for the echo clocks are shown in the
Switching Characteristics on
page 24.
Synchronous Echo Clock Outputs.
This is a free running clock and is synchronized to the input clock
(K) of the QDR II+ Xtreme.The timings for the echo clocks are shown in the
Switching Characteristics on
page 24.
Output Impedance Matching Input.
This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ, and Q
[x:0]
output impedance are set to 0.2 × RQ, where RQ is a resistor connected
between ZQ and ground. Alternatively, this pin can be connected directly to V
DDQ
, which enables the
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
PLL Turn Off
Active LOW.
Connecting this pin to ground turns off the PLL inside the device. The timings
in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin
can be connected to a pull up through a 10 K or less pull up resistor. The device behaves in QDR I mode
when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz
with QDR I timing.
WPS
BWS
0
,
BWS
1
,
BWS
2
,
BWS
3
A
Q
[x:0]
RPS
QVLD
K
K
CQ
CQ
Echo Clock
ZQ
Input
DOFF
Input
Document Number: 001-70328 Rev. *F
Page 5 of 30
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