MPC92432FA datasheet, PDF - EEWORLD Datasheet

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MPC92432FA: DescriptionClock Generator, 1360MHz, PQFP48, LQFP-48; CategoryThe embedded processor and controller Microcontrollers and processors; File Size430KB，19 Pages; ManufacturerIDT (Integrated Device Technology)

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MPC92432FA Overview

Clock Generator, 1360MHz, PQFP48, LQFP-48

MPC92432FA Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	LFQFP, QFP48,.35SQ,20
Contacts	48
Reach Compliance Code	_compli
ECCN code	EAR99
JESD-30 code	S-PQFP-G48
JESD-609 code	e0
length	7 mm
Humidity sensitivity level	3
Number of terminals	48
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Maximum output clock frequency	1360 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP48,.35SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	240
power supply	3.3 V
Master clock/crystal nominal frequency	20 MHz
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum slew rate	150 mA
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	7 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER

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Freescale Semiconductor

Technical Data

DATA SHEET

MPC92432

Rev 2, 06/2005

1360 MHz Dual Output LVPECL

1360 MHz Dual

Clock Synthesizer

Output LVPECL Clock

MPC92432

Synthesizer

MPC92432

NRND

The MPC92432 is a 3.3 V compatible, PLL based clock synthesizer targeted

for high performance clock generation in mid-range to high-performance

telecom, networking, and computing applications. With output frequencies from

21.25 MHz to 1360 MHz and the support of two differential PECL output signals,

the device meets the needs of the most demanding clock applications.

Features

• 21.25 MHz to 1360 MHz synthesized clock output signal

• Two differential, LVPECL-compatible high-frequency outputs

• Output frequency programmable through 2-wire I

C bus or parallel interface

• On-chip crystal oscillator for reference frequency generation

• Alternative LVCMOS compatible reference clock input

• Synchronous clock stop functionality for both outputs

• LOCK indicator output (LVCMOS)

• LVCMOS compatible control inputs

• Fully integrated PLL

• 3.3-V power supply

• 48-lead LQFP

• 48-lead Pb-free package available

• SiGe Technology

• Ambient temperature range: –40°C to +85°C

• NOT RECOMMENDED FOR NEW DESIGNS

Applications

• Programmable clock source for server, computing, and telecommunication systems

• Frequency margining

• Oscillator replacement

Functional Description

1360 MHz LOW VOLTAGE

CLOCK SYNTHESIZER

FA SUFFIX

(1)

48-LEAD LQFP PACKAGE

CASE 932-03

AE SUFFIX

(2)

48-LEAD LQFP PACKAGE

Pb-FREE PACKAGE

CASE 932-03

The MPC92432 is a programmable high-frequency clock source (clock synthesizer). The internal PLL generates a high-

frequency output signal based on a low-frequency reference signal. The frequency of the output signal is programmable and can

be changed on the fly for frequency margining purpose.

The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. Alternatively, a LVCMOS

compatible clock signal can be used as a PLL reference signal. The frequency of the internal crystal oscillator is divided by a

selectable divider and then multiplied by the PLL. The VCO within the PLL operates over a range of 1360 to 2720 MHz. Its output

is scaled by a divider that is configured by either the I

C or parallel interfaces. The crystal oscillator frequency f

XTAL

, the PLL pre-

divider P, the feedback-divider M, and the PLL post-divider N determine the output frequency. The feedback path of the PLL is

internal.

The PLL post-divider N is configured through either the I

C or the parallel interfaces, and can provide one of six division ratios

(2, 4, 8, 16, 32, 64). This divider extends the performance of the part while providing a 50% duty cycle. The high-frequency out-

puts, Q

and Q

, are differential and are capable of driving a pair of transmission lines terminated 50

Ω

to V

– 2.0 V. The second

high-frequency output, Q

, can be configured to run at either 1x or 1/2x of the clock frequency or the first output (Q

). The positive

supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize noise

induced jitter.

The configuration logic has two sections: I

C and parallel. The parallel interface uses the values at the M[9:0], NA[2:0], NB,

and P parallel inputs to configure the internal PLL dividers. The parallel programming interface has priority over the serial I

interface. The serial interface is I

C compatible and provides read and write access to the internal PLL configuration registers.

The lock state of the PLL is indicated by the LVCMOS-compatible LOCK output.

1. FA suffix: leaded terminations.

2. AE suffix: lead-free, EPP and RoHS-compliant.

IDT™

1360 MHz Dual Output LVPECL Clock Synthesizer

MPC92432

acquired by Integrated Device Technology, Inc

Freescale Timing Solutions Organization has been

rights reserved.

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